Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
shregmap_maxlen.ys
blob: b537476210013f5a100c8a745c68fc32db063713 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
tech greenpak4
-
maxlen
10
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v
