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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
Zachjs
/
basic
/
part_select.sv
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module
top
;
wire
[
31
:
0
]
a
;
wire
[
0
:
31
]
b
;
assign a
=
'h64ded943;
assign b = '
hb7151d17
;
initial
begin
$display
(
a
[
0
+:
8
]);
$display
(
a
[
15
-:
8
]);
$display
(
b
[
0
+:
8
]);
$display
(
b
[
15
-:
8
]);
end
endmodule