| commit | 42a29a10e64ddf11a439af33ef5766aec01d3e53 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Sat Nov 16 14:06:09 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Sat Nov 16 14:06:09 2019 -0800 |
| tree | 75f5eb7a5a2fc7f0fb87cb6c32983eb23fad75bf | |
| parent | 7f33cfad4f75d76cd8c8bdf0b313ea5b00658606 [diff] |
Remove _config.yml; accientally submitted.
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output