blob: 54e84dbabb4c7befaa8ce9b85c2eebd1b3a9aa07 [file] [log] [blame]
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* SURELOG System Verilog Compiler/Linter *
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|-------|------------------|-------------------|
| | FILE UNIT COMP | ALL COMPILATION |
|-------|------------------|-------------------|
| FATAL | 0 | 0 |
| ERROR | 30 | 32 |
|WARNING| 19 | 11 |
| INFO | | |
| NOTE | 12 | 26 |
|-------|------------------|-------------------|
FILE UNIT LOG: ./slpp_unit/surelog.log
ALL FILES LOG: ./slpp_all/surelog.log
DIFFS:
./slpp_unit/work/top_3.v and ./slpp_all/work/top_3.v
./slpp_unit/work/top_4.v and ./slpp_all/work/top_4.v
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* End SURELOG SVerilog Compiler/Linter *
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1.00user 0.05system 0:01.34elapsed 78%CPU (0avgtext+0avgdata 49940maxresident)k
1424inputs+368outputs (2major+21749minor)pagefaults 0swaps