Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
4563acfd6b0b2e2137e28206273e5813fa6cdec7
/
.
/
SVIncCompil
/
Testcases
/
Yosys
/
opt
/
opt_lut.ys
blob: a9fccbb624c05e4d47e0baf73573977396025abd [
file
]
read_verilog opt_lut
.
v
equiv_opt
-
map
+
/ice40/
cells_sim
.
v
-
assert
synth_ice40
