Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
4563acfd6b0b2e2137e28206273e5813fa6cdec7
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00987
/
top.v
blob: db72c610e6c840d38e21161ef7efb911aa87a7b9 [
file
]
module
test
(
output
var
a
,
input b
);
always_comb a
=
b
;
endmodule