cleanup diff files
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes_diff.log b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes_diff.log deleted file mode 100644 index e867e08..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes_diff.log +++ /dev/null
@@ -1,45 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/aes_cipher_top.v:48 Compile module "work@aes_cipher_top". - -[INFO :CP0303] rtl/aes_key_expand_128.v:42 Compile module "work@aes_key_expand_128". - -[INFO :CP0303] rtl/aes_sbox.v:43 Compile module "work@aes_sbox". - -[INFO :CP0303] rtl/aes_rcon.v:42 Compile module "work@aes_rcon". - -[INFO :CP0303] sim/bench.v:70 Compile module "work@testbench". - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] sim/bench.v:70 Top level module "work@testbench". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 4. - -[NOTE :EL0510] Nb instances: 44. - -[NOTE :EL0511] Nb leaf instances: 40. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 0 -[ NOTE] : 5 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -2.90user 0.08system 0:01.63elapsed 183%CPU (0avgtext+0avgdata 72800maxresident)k -168inputs+264outputs (0major+15518minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/YosysBigSimAmber23_diff.log b/SVIncCompil/Testcases/YosysBigSim/amber23/YosysBigSimAmber23_diff.log deleted file mode 100644 index 8b7b0cc..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/amber23/YosysBigSimAmber23_diff.log +++ /dev/null
@@ -1,157 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PA0207] rtl/a23_decode.v:174 Syntax error: mismatched input 'type' expecting {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier}, -reg [3:0] type; - ^-- ./slpp_unit/work/rtl/a23_decode.v:518 col:23. - -[WARNI:PA0205] rtl/a23_barrel_shift.v:42 No timescale set for "a23_barrel_shift". - -[WARNI:PA0205] rtl/a23_decompile.v:44 No timescale set for "a23_decompile". - -[WARNI:PA0205] rtl/a23_fetch.v:45 No timescale set for "a23_fetch". - -[WARNI:PA0205] rtl/a23_alu.v:43 No timescale set for "a23_alu". - -[WARNI:PA0205] rtl/a23_barrel_shift_fpga.v:46 No timescale set for "a23_barrel_shift_fpga". - -[WARNI:PA0205] rtl/a23_core.v:43 No timescale set for "a23_core". - -[WARNI:PA0205] rtl/a23_coprocessor.v:41 No timescale set for "a23_coprocessor". - -[WARNI:PA0205] rtl/a23_multiply.v:56 No timescale set for "a23_multiply". - -[WARNI:PA0205] rtl/a23_register_bank.v:44 No timescale set for "a23_register_bank". - -[WARNI:PA0205] rtl/a23_execute.v:45 No timescale set for "a23_execute". - -[WARNI:PA0205] rtl/generic_sram_byte_en.v:43 No timescale set for "generic_sram_byte_en". - -[WARNI:PA0205] rtl/a23_wishbone.v:58 No timescale set for "a23_wishbone". - -[WARNI:PA0205] rtl/generic_sram_line_en.v:42 No timescale set for "generic_sram_line_en". - -[WARNI:PA0205] rtl/a23_decode.v:43 No timescale set for "a23_decode". - -[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench". - -[WARNI:PA0205] rtl/a23_cache.v:47 No timescale set for "a23_cache". - -[WARNI:PA0205] rtl/a23_ram_register_bank.v:44 No timescale set for "a23_ram_register_bank". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/a23_alu.v:43 Compile module "work@a23_alu". - -[INFO :CP0303] rtl/a23_barrel_shift.v:42 Compile module "work@a23_barrel_shift". - -[INFO :CP0303] rtl/a23_cache.v:47 Compile module "work@a23_cache". - -[INFO :CP0303] rtl/a23_barrel_shift_fpga.v:46 Compile module "work@a23_barrel_shift_fpga". - -[INFO :CP0303] rtl/a23_coprocessor.v:41 Compile module "work@a23_coprocessor". - -[INFO :CP0303] rtl/a23_execute.v:45 Compile module "work@a23_execute". - -[INFO :CP0303] rtl/a23_decode.v:43 Compile module "work@a23_decode". - -[INFO :CP0303] rtl/a23_decompile.v:44 Compile module "work@a23_decompile". - -[INFO :CP0303] rtl/a23_ram_register_bank.v:44 Compile module "work@a23_ram_register_bank". - -[INFO :CP0303] rtl/a23_register_bank.v:44 Compile module "work@a23_register_bank". - -[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench". - -[INFO :CP0303] rtl/generic_sram_line_en.v:42 Compile module "work@generic_sram_line_en". - -[INFO :CP0303] rtl/a23_core.v:43 Compile module "work@a23_core". - -[INFO :CP0303] rtl/a23_fetch.v:45 Compile module "work@a23_fetch". - -[INFO :CP0303] rtl/a23_multiply.v:56 Compile module "work@a23_multiply". - -[INFO :CP0303] rtl/a23_wishbone.v:58 Compile module "work@a23_wishbone". - -[INFO :CP0303] rtl/generic_sram_byte_en.v:43 Compile module "work@generic_sram_byte_en". - -[NOTE :CP0309] rtl/a23_alu.v:51 Implicit port type (wire) for "o_out", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/a23_coprocessor.v:58 Implicit port type (wire) for "o_cache_enable", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/a23_execute.v:63 Implicit port type (wire) for "o_address_nxt", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/a23_register_bank.v:71 Implicit port type (wire) for "o_rm", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/a23_barrel_shift.v:50 Implicit port type (wire) for "o_out", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/a23_core.v:53 Implicit port type (wire) for "o_wb_adr", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/a23_fetch.v:54 Implicit port type (wire) for "o_read_data", -there are 7 more instances of this message. - -[NOTE :CP0309] rtl/a23_wishbone.v:70 Implicit port type (wire) for "o_stall". - -[NOTE :CP0309] rtl/a23_barrel_shift_fpga.v:54 Implicit port type (wire) for "o_out", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/a23_decode.v:81 Implicit port type (wire) for "o_rm_sel_nxt", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/a23_multiply.v:65 Implicit port type (wire) for "o_out", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/a23_cache.v:98 Implicit port type (wire) for "o_read_data", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/a23_ram_register_bank.v:69 Implicit port type (wire) for "o_rm", -there are 4 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] rtl/a23_decompile.v:44 Top level module "work@a23_decompile". - -[NOTE :EL0503] rtl/a23_barrel_shift_fpga.v:46 Top level module "work@a23_barrel_shift_fpga". - -[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench". - -[NOTE :EL0503] rtl/a23_ram_register_bank.v:44 Top level module "work@a23_ram_register_bank". - -[NOTE :EL0504] Multiple top level modules in design. - -[ERROR:EL0514] rtl/a23_decode.v:806 Undefined variable: instruction. - -[ERROR:EL0514] rtl/a23_decode.v:832 Undefined variable: instruction. - -[NOTE :EL0508] Nb Top level modules: 4. - -[NOTE :EL0509] Max instance depth: 6. - -[NOTE :EL0510] Nb instances: 23. - -[NOTE :EL0511] Nb leaf instances: 3. - -[ FATAL] : 0 -[ ERROR] : 3 -[WARNING] : 17 -[ NOTE] : 22 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -10.32user 0.25system 0:03.33elapsed 317%CPU (0avgtext+0avgdata 200992maxresident)k -0inputs+1392outputs (0major+47527minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/elliptic_curve_group/YosysBigSimEllip_diff.log b/SVIncCompil/Testcases/YosysBigSim/elliptic_curve_group/YosysBigSimEllip_diff.log deleted file mode 100644 index 1e69460..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/elliptic_curve_group/YosysBigSimEllip_diff.log +++ /dev/null
@@ -1,191 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[WARNI:PA0205] rtl/f3m.v:26 No timescale set for "f3m_mux3". - -[WARNI:PA0205] rtl/f3m.v:40 No timescale set for "f3m_mux6". - -[WARNI:PA0205] rtl/f3m.v:54 No timescale set for "f3m_add". - -[WARNI:PA0205] rtl/f3m.v:66 No timescale set for "f3m_add3". - -[WARNI:PA0205] rtl/f3m.v:76 No timescale set for "f3m_add4". - -[WARNI:PA0205] rtl/f3m.v:87 No timescale set for "f3m_neg". - -[WARNI:PA0205] rtl/f3m.v:100 No timescale set for "f3m_sub". - -[WARNI:PA0205] rtl/f3m.v:112 No timescale set for "f3m_mult". - -[WARNI:PA0205] rtl/f3m.v:157 No timescale set for "f3m_mult3". - -[WARNI:PA0205] rtl/f3m.v:212 No timescale set for "f3m_cubic". - -[WARNI:PA0205] rtl/f3m.v:474 No timescale set for "f3m_nine". - -[WARNI:PA0205] rtl/f3m.v:487 No timescale set for "f3m_inv". - -[WARNI:PA0205] rtl/f3m.v:560 No timescale set for "func1". - -[WARNI:PA0205] rtl/f3m.v:573 No timescale set for "func2". - -[WARNI:PA0205] rtl/f3m.v:580 No timescale set for "func3". - -[WARNI:PA0205] rtl/f3m.v:597 No timescale set for "func4". - -[WARNI:PA0205] rtl/f3m.v:611 No timescale set for "func5". - -[WARNI:PA0205] rtl/f3m.v:623 No timescale set for "func7". - -[WARNI:PA0205] rtl/f3m.v:639 No timescale set for "func8". - -[WARNI:PA0205] rtl/f3.v:22 No timescale set for "f3_add". - -[WARNI:PA0205] rtl/f3.v:38 No timescale set for "f3_sub". - -[WARNI:PA0205] rtl/f3.v:45 No timescale set for "f3_mult". - -[WARNI:PA0205] rtl/f3.v:57 No timescale set for "f3_add1". - -[WARNI:PA0205] rtl/f3.v:65 No timescale set for "f3_sub1". - -[WARNI:PA0205] rtl/fun.v:24 No timescale set for "func6". - -[WARNI:PA0205] sim/bench.v:1 No timescale set for "testbench". - -[WARNI:PA0205] rtl/ecg.v:25 No timescale set for "point_scalar_mult". - -[WARNI:PA0205] rtl/ecg.v:86 No timescale set for "point_add". - -[WARNI:PA0205] rtl/ecg.v:163 No timescale set for "func9". - -[WARNI:PA0205] rtl/ecg.v:184 No timescale set for "func10". - -[WARNI:PA0205] rtl/ecg.v:226 No timescale set for "func11". - -[WARNI:PA0205] sim/test_point_add.v:3 No timescale set for "test_point_add". - -[WARNI:PA0205] sim/test_point_scalar_mult.v:3 No timescale set for "test_point_scalar_mult". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/f3.v:22 Compile module "work@f3_add". - -[INFO :CP0303] rtl/f3.v:45 Compile module "work@f3_mult". - -[INFO :CP0303] rtl/f3.v:57 Compile module "work@f3_add1". - -[INFO :CP0303] rtl/f3.v:38 Compile module "work@f3_sub". - -[INFO :CP0303] rtl/f3m.v:54 Compile module "work@f3m_add". - -[INFO :CP0303] rtl/f3.v:65 Compile module "work@f3_sub1". - -[INFO :CP0303] rtl/f3m.v:66 Compile module "work@f3m_add3". - -[INFO :CP0303] rtl/f3m.v:76 Compile module "work@f3m_add4". - -[INFO :CP0303] rtl/f3m.v:112 Compile module "work@f3m_mult". - -[INFO :CP0303] rtl/f3m.v:157 Compile module "work@f3m_mult3". - -[INFO :CP0303] rtl/f3m.v:487 Compile module "work@f3m_inv". - -[INFO :CP0303] rtl/f3m.v:474 Compile module "work@f3m_nine". - -[INFO :CP0303] rtl/f3m.v:40 Compile module "work@f3m_mux6". - -[INFO :CP0303] rtl/ecg.v:226 Compile module "work@func11". - -[INFO :CP0303] rtl/f3m.v:560 Compile module "work@func1". - -[INFO :CP0303] rtl/f3m.v:611 Compile module "work@func5". - -[INFO :CP0303] rtl/f3m.v:580 Compile module "work@func3". - -[INFO :CP0303] rtl/ecg.v:163 Compile module "work@func9". - -[INFO :CP0303] rtl/f3m.v:623 Compile module "work@func7". - -[INFO :CP0303] rtl/f3m.v:212 Compile module "work@f3m_cubic". - -[INFO :CP0303] sim/test_point_scalar_mult.v:3 Compile module "work@test_point_scalar_mult". - -[INFO :CP0303] rtl/ecg.v:25 Compile module "work@point_scalar_mult". - -[INFO :CP0303] rtl/f3m.v:26 Compile module "work@f3m_mux3". - -[INFO :CP0303] rtl/f3m.v:87 Compile module "work@f3m_neg". - -[INFO :CP0303] rtl/ecg.v:184 Compile module "work@func10". - -[INFO :CP0303] rtl/f3m.v:100 Compile module "work@f3m_sub". - -[INFO :CP0303] rtl/f3m.v:597 Compile module "work@func4". - -[INFO :CP0303] rtl/f3m.v:573 Compile module "work@func2". - -[INFO :CP0303] rtl/f3m.v:639 Compile module "work@func8". - -[INFO :CP0303] rtl/fun.v:24 Compile module "work@func6". - -[INFO :CP0303] rtl/ecg.v:86 Compile module "work@point_add". - -[INFO :CP0303] sim/bench.v:1 Compile module "work@testbench". - -[INFO :CP0303] sim/test_point_add.v:3 Compile module "work@test_point_add". - -[NOTE :CP0309] rtl/f3.v:22 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3.v:65 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3m.v:26 Implicit port type (wire) for "out". - -[NOTE :CP0309] rtl/f3m.v:100 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3m.v:573 Implicit port type (wire) for "out". - -[NOTE :CP0309] rtl/fun.v:24 Implicit port type (wire) for "out". - -[NOTE :CP0309] rtl/f3.v:57 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3m.v:54 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3m.v:40 Implicit port type (wire) for "out". - -[NOTE :CP0309] rtl/f3m.v:560 Implicit port type (wire) for "out". - -[NOTE :CP0309] rtl/f3m.v:580 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3.v:45 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3m.v:66 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3m.v:87 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3m.v:597 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3m.v:639 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3.v:38 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/f3m.v:76 Implicit port type (wire) for "c". - -[NOTE :CP0309] rtl/f3m.v:611 Implicit port type (wire) for "C". - -[NOTE :CP0309] rtl/ecg.v:163 Implicit port type (wire) for "x3", -there are 2 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -/home/alain/surelog/SVIncCompil/dist/surelog/surelog: line 5: 13357 Killed ${SCRIPTPATH}/bin/surelog.exe "$@" -Command exited with non-zero status 137 -152.87user 4.77system 9:38.96elapsed 27%CPU (0avgtext+0avgdata 6572516maxresident)k -14016inputs+408outputs (108major+1853053minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/YosysBigSimLm32_diff.log b/SVIncCompil/Testcases/YosysBigSim/lm32/YosysBigSimLm32_diff.log deleted file mode 100644 index 56a118e..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/lm32/YosysBigSimLm32_diff.log +++ /dev/null
@@ -1,202 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0107] rtl/lm32_dcache.v:118 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_dcache.v:119 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_dcache.v:129 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_dtlb.v:89 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_dtlb.v:90 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_icache.v:128 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_icache.v:129 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_icache.v:139 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_instruction_unit.v:196 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_itlb.v:88 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_itlb.v:89 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[ERROR:PP0107] rtl/lm32_load_store_unit.v:159 Too many arguments (1) for macro "CLOG2", - ./rtl/lm32_config.v:57 macro definition takes 0. - -[WARNI:PA0205] rtl/lm32_addsub.v:54 No timescale set for "lm32_addsub". - -[WARNI:PA0205] rtl/lm32_adder.v:55 No timescale set for "lm32_adder". - -[WARNI:PA0205] rtl/lm32_decoder.v:65 No timescale set for "lm32_decoder". - -[WARNI:PA0205] rtl/lm32_debug.v:61 No timescale set for "lm32_debug". - -[WARNI:PA0205] rtl/lm32_dcache.v:62 No timescale set for "lm32_dcache". - -[WARNI:PA0205] rtl/lm32_icache.v:67 No timescale set for "lm32_icache". - -[WARNI:PA0205] rtl/lm32_dp_ram.v:36 No timescale set for "lm32_dp_ram". - -[WARNI:PA0205] rtl/lm32_dtlb.v:41 No timescale set for "lm32_dtlb". - -[WARNI:PA0205] rtl/lm32_itlb.v:40 No timescale set for "lm32_itlb". - -[WARNI:PA0205] rtl/lm32_logic_op.v:55 No timescale set for "lm32_logic_op". - -[WARNI:PA0205] rtl/lm32_multiplier.v:55 No timescale set for "lm32_multiplier". - -[WARNI:PA0205] rtl/lm32_shifter.v:55 No timescale set for "lm32_shifter". - -[WARNI:PA0205] rtl/lm32_interrupt.v:55 No timescale set for "lm32_interrupt". - -[WARNI:PA0205] rtl/lm32_instruction_unit.v:76 No timescale set for "lm32_instruction_unit". - -[WARNI:PA0205] rtl/lm32_mc_arithmetic.v:56 No timescale set for "lm32_mc_arithmetic". - -[WARNI:PA0205] rtl/lm32_ram.v:60 No timescale set for "lm32_ram". - -[WARNI:PA0205] rtl/lm32_top.v:55 No timescale set for "lm32_top". - -[WARNI:PA0205] rtl/lm32_load_store_unit.v:68 No timescale set for "lm32_load_store_unit". - -[WARNI:PA0205] rtl/lm32_cpu.v:98 No timescale set for "lm32_cpu". - -[WARNI:PA0205] sim/tb_lm32_system.v:33 No timescale set for "testbench". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/lm32_adder.v:55 Compile module "work@lm32_adder". - -[INFO :CP0303] rtl/lm32_cpu.v:98 Compile module "work@lm32_cpu". - -[INFO :CP0303] rtl/lm32_addsub.v:54 Compile module "work@lm32_addsub". - -[INFO :CP0303] rtl/lm32_dcache.v:62 Compile module "work@lm32_dcache". - -[INFO :CP0303] rtl/lm32_debug.v:61 Compile module "work@lm32_debug". - -[INFO :CP0303] rtl/lm32_decoder.v:65 Compile module "work@lm32_decoder". - -[INFO :CP0303] rtl/lm32_icache.v:67 Compile module "work@lm32_icache". - -[INFO :CP0303] rtl/lm32_dtlb.v:41 Compile module "work@lm32_dtlb". - -[INFO :CP0303] rtl/lm32_load_store_unit.v:68 Compile module "work@lm32_load_store_unit". - -[INFO :CP0303] rtl/lm32_itlb.v:40 Compile module "work@lm32_itlb". - -[INFO :CP0303] rtl/lm32_instruction_unit.v:76 Compile module "work@lm32_instruction_unit". - -[INFO :CP0303] rtl/lm32_multiplier.v:55 Compile module "work@lm32_multiplier". - -[INFO :CP0303] sim/tb_lm32_system.v:33 Compile module "work@testbench". - -[INFO :CP0303] rtl/lm32_dp_ram.v:36 Compile module "work@lm32_dp_ram". - -[INFO :CP0303] rtl/lm32_ram.v:60 Compile module "work@lm32_ram". - -[INFO :CP0303] rtl/lm32_interrupt.v:55 Compile module "work@lm32_interrupt". - -[INFO :CP0303] rtl/lm32_logic_op.v:55 Compile module "work@lm32_logic_op". - -[INFO :CP0303] rtl/lm32_mc_arithmetic.v:56 Compile module "work@lm32_mc_arithmetic". - -[INFO :CP0303] rtl/lm32_shifter.v:55 Compile module "work@lm32_shifter". - -[INFO :CP0303] rtl/lm32_top.v:55 Compile module "work@lm32_top". - -[NOTE :CP0309] rtl/lm32_adder.v:62 Implicit port type (wire) for "adder_result_x", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/lm32_debug.v:81 Implicit port type (wire) for "bp_match", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/lm32_icache.v:83 Implicit port type (wire) for "stall_request", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/lm32_load_store_unit.v:106 Implicit port type (wire) for "dcache_refill_request", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/lm32_ram.v:72 Implicit port type (wire) for "read_data". - -[NOTE :CP0309] rtl/lm32_addsub.v:61 Implicit port type (wire) for "Result", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/lm32_decoder.v:80 Implicit port type (wire) for "x_bypass_enable", -there are 28 more instances of this message. - -[NOTE :CP0309] rtl/lm32_instruction_unit.v:116 Implicit port type (wire) for "icache_stall_request", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/lm32_shifter.v:65 Implicit port type (wire) for "shifter_result_m". - -[NOTE :CP0309] rtl/lm32_cpu.v:118 Implicit port type (wire) for "I_DAT_O", -there are 17 more instances of this message. - -[NOTE :CP0309] rtl/lm32_dp_ram.v:49 Implicit port type (wire) for "do_a", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/lm32_interrupt.v:71 Implicit port type (wire) for "interrupt_exception". - -[NOTE :CP0309] rtl/lm32_mc_arithmetic.v:69 Implicit port type (wire) for "stall_request_x". - -[NOTE :CP0309] rtl/lm32_top.v:75 Implicit port type (wire) for "I_DAT_O", -there are 17 more instances of this message. - -[NOTE :CP0309] rtl/lm32_dcache.v:80 Implicit port type (wire) for "stall_request", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/lm32_dtlb.v:62 Implicit port type (wire) for "physical_load_store_address_m", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/lm32_itlb.v:60 Implicit port type (wire) for "stall_request", -there are 2 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] rtl/lm32_dp_ram.v:36 Top level module "work@lm32_dp_ram". - -[NOTE :EL0503] sim/tb_lm32_system.v:33 Top level module "work@testbench". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 2. - -[NOTE :EL0509] Max instance depth: 8. - -[NOTE :EL0510] Nb instances: 27. - -[NOTE :EL0511] Nb leaf instances: 10. - -[ FATAL] : 0 -[ ERROR] : 12 -[WARNING] : 20 -[ NOTE] : 24 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -14.59user 0.33system 0:04.97elapsed 300%CPU (0avgtext+0avgdata 273116maxresident)k -816inputs+1200outputs (0major+65714minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/YosysBigSimOpenMsp_diff.log b/SVIncCompil/Testcases/YosysBigSim/openmsp430/YosysBigSimOpenMsp_diff.log deleted file mode 100644 index 1d3a3d4..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/YosysBigSimOpenMsp_diff.log +++ /dev/null
@@ -1,229 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH". - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE". - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH". - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE". - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH". - -[WARNI:PP0103] ./rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:626 Unknown macro "PER_SIZE". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:629 Unknown macro "PMEM_AWIDTH". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:630 Unknown macro "DMEM_AWIDTH". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:631 Unknown macro "PER_AWIDTH". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_DCO_FREQ". - -[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_UART_BAUD". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH". - -[WARNI:PP0103] rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE". - -[ERROR:PA0207] sim/sieve.v:1 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[', -pmem[ 512] = 16'h4031; - ^-- ./slpp_unit/work/sim/sieve.v:1 col:4. - -[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate". - -[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate". - -[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux". - -[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk". - -[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module". - -[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu". - -[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg". - -[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit". - -[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file". - -[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430". - -[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart". - -[WARNI:PA0205] rtl/omsp_dbg_i2c.v:46 No timescale set for "omsp_dbg_i2c". - -[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone". - -[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset". - -[WARNI:PA0205] rtl/omsp_wakeup_cell.v:46 No timescale set for "omsp_wakeup_cell". - -[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier". - -[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell". - -[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog". - -[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend". - -[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux". - -[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu". - -[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate". - -[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate". - -[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module". - -[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg". - -[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk". - -[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux". - -[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart". - -[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend". - -[INFO :CP0303] rtl/omsp_dbg_i2c.v:46 Compile module "work@omsp_dbg_i2c". - -[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier". - -[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit". - -[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone". - -[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell". - -[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430". - -[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr". - -[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file". - -[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux". - -[INFO :CP0303] rtl/omsp_wakeup_cell.v:46 Compile module "work@omsp_wakeup_cell". - -[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog". - -[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset". - -[INFO :CP0303] sim/bench.v:6 Compile module "work@testbench". - -[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out". - -[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout". - -[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out". - -[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk", -there are 25 more instances of this message. - -[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y". - -[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_cpu_reset", -there are 9 more instances of this message. - -[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff", -there are 9 more instances of this message. - -[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s". - -[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk". - -[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out". - -[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk", -there are 14 more instances of this message. - -[NOTE :CP0309] rtl/omsp_dbg_i2c.v:50 Implicit port type (wire) for "dbg_din". - -[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din", -there are 15 more instances of this message. - -[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout", -there are 3 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate". - -[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate". - -[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux". - -[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk". - -[NOTE :EL0503] rtl/omsp_dbg_i2c.v:46 Top level module "work@omsp_dbg_i2c". - -[NOTE :EL0503] rtl/omsp_wakeup_cell.v:46 Top level module "work@omsp_wakeup_cell". - -[NOTE :EL0503] sim/bench.v:6 Top level module "work@testbench". - -[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 8. - -[NOTE :EL0509] Max instance depth: 5. - -[NOTE :EL0510] Nb instances: 27. - -[NOTE :EL0511] Nb leaf instances: 17. - -[ FATAL] : 0 -[ ERROR] : 7 -[WARNING] : 33 -[ NOTE] : 33 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -11.49user 0.55system 0:04.15elapsed 290%CPU (0avgtext+0avgdata 225912maxresident)k -0inputs+2872outputs (0major+53779minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/YosysBigSimReed_diff.log b/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/YosysBigSimReed_diff.log deleted file mode 100644 index 1f82592..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/YosysBigSimReed_diff.log +++ /dev/null
@@ -1,109 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0125] Cannot read the file's content "rtl/BM_lamda.v". Only UTF-8 is supported. - -[WARNI:PA0205] rtl/GF_matrix_ascending_binary.v:20 No timescale set for "GF_matrix_ascending_binary". - -[WARNI:PA0205] rtl/GF_matrix_dec.v:21 No timescale set for "GF_matrix_dec". - -[WARNI:PA0205] rtl/DP_RAM.v:18 No timescale set for "DP_RAM". - -[WARNI:PA0205] rtl/GF_mult_add_syndromes.v:28 No timescale set for "GF_mult_add_syndromes". - -[WARNI:PA0205] rtl/input_syndromes.v:24 No timescale set for "input_syndromes". - -[WARNI:PA0205] rtl/RS_dec.v:21 No timescale set for "RS_dec". - -[WARNI:PA0205] rtl/Omega_Phy.v:21 No timescale set for "Omega_Phy". - -[WARNI:PA0205] rtl/transport_in2out.v:22 No timescale set for "transport_in2out". - -[WARNI:PA0205] rtl/error_correction.v:20 No timescale set for "error_correction". - -[WARNI:PA0205] rtl/lamda_roots.v:21 No timescale set for "lamda_roots". - -[WARNI:PA0205] rtl/out_stage.v:21 No timescale set for "out_stage". - -[WARNI:PA0205] sim/RS_dec_tb.v:3 No timescale set for "testbench". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/DP_RAM.v:18 Compile module "work@DP_RAM". - -[INFO :CP0303] rtl/GF_matrix_ascending_binary.v:20 Compile module "work@GF_matrix_ascending_binary". - -[INFO :CP0303] rtl/GF_mult_add_syndromes.v:28 Compile module "work@GF_mult_add_syndromes". - -[INFO :CP0303] rtl/GF_matrix_dec.v:21 Compile module "work@GF_matrix_dec". - -[INFO :CP0303] rtl/Omega_Phy.v:21 Compile module "work@Omega_Phy". - -[INFO :CP0303] rtl/RS_dec.v:21 Compile module "work@RS_dec". - -[INFO :CP0303] rtl/input_syndromes.v:24 Compile module "work@input_syndromes". - -[INFO :CP0303] rtl/error_correction.v:20 Compile module "work@error_correction". - -[INFO :CP0303] rtl/lamda_roots.v:21 Compile module "work@lamda_roots". - -[INFO :CP0303] rtl/out_stage.v:21 Compile module "work@out_stage". - -[INFO :CP0303] rtl/transport_in2out.v:22 Compile module "work@transport_in2out". - -[INFO :CP0303] sim/RS_dec_tb.v:3 Compile module "work@testbench". - -[NOTE :CP0309] rtl/Omega_Phy.v:44 Implicit port type (wire) for "add_pow2", -there are 20 more instances of this message. - -[NOTE :CP0309] rtl/lamda_roots.v:30 Implicit port type (wire) for "add_GF_dec1", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/RS_dec.v:29 Implicit port type (wire) for "Out_byte", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/error_correction.v:44 Implicit port type (wire) for "add_pow2", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/input_syndromes.v:38 Implicit port type (wire) for "s1", -there are 15 more instances of this message. - -[NOTE :CP0309] rtl/transport_in2out.v:32 Implicit port type (wire) for "WE", -there are 1 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] sim/RS_dec_tb.v:3 Top level module "work@testbench". - -[WARNI:EL0500] rtl/RS_dec.v:106 Cannot find a module definition for "work@RS_dec::BM_lamda". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 5. - -[NOTE :EL0510] Nb instances: 26. - -[NOTE :EL0511] Nb leaf instances: 1. - -[WARNI:EL0512] Nb undefined modules: 1. - -[WARNI:EL0513] Nb undefined instances: 1. - -[ FATAL] : 0 -[ ERROR] : 1 -[WARNING] : 15 -[ NOTE] : 11 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -5.60user 0.12system 0:01.95elapsed 293%CPU (0avgtext+0avgdata 111632maxresident)k -256inputs+320outputs (0major+25202minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/YosysBigSimSoft_diff.log b/SVIncCompil/Testcases/YosysBigSim/softusb_navre/YosysBigSimSoft_diff.log deleted file mode 100644 index 3fc6911..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/YosysBigSimSoft_diff.log +++ /dev/null
@@ -1,46 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench". - -[WARNI:PA0205] rtl/softusb_navre.v:18 No timescale set for "softusb_navre". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/softusb_navre.v:18 Compile module "work@softusb_navre". - -[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench". - -[NOTE :CP0309] rtl/softusb_navre.v:26 Implicit port type (wire) for "pmem_a", -there are 2 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 2. - -[NOTE :EL0510] Nb instances: 2. - -[NOTE :EL0511] Nb leaf instances: 0. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 2 -[ NOTE] : 6 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.02user 0.06system 0:02.23elapsed 138%CPU (0avgtext+0avgdata 98488maxresident)k -64inputs+120outputs (0major+21952minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/YosysBigSimPong_diff.log b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/YosysBigSimPong_diff.log deleted file mode 100644 index e7fd734..0000000 --- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/YosysBigSimPong_diff.log +++ /dev/null
@@ -1,70 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[WARNI:PP0103] sim/bench.v:5 Undefining an unknown macro "WRITE_FRAMES_PPM". - -[WARNI:PA0205] rtl/data.v:1 No timescale set for "font_rom". - -[WARNI:PA0205] rtl/text_graph.v:1 No timescale set for "text_graph". - -[WARNI:PA0205] rtl/vga_sync.v:1 No timescale set for "vga_sync". - -[WARNI:PA0205] sim/bench.v:7 No timescale set for "testbench". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/debounce.v:3 Compile module "work@debounce". - -[INFO :CP0303] rtl/data.v:1 Compile module "work@font_rom". - -[INFO :CP0303] rtl/pong_graph.v:3 Compile module "work@pong_graph". - -[INFO :CP0303] sim/bench.v:7 Compile module "work@testbench". - -[INFO :CP0303] rtl/text_graph.v:1 Compile module "work@text_graph". - -[INFO :CP0303] rtl/vga_sync.v:1 Compile module "work@vga_sync". - -[INFO :CP0303] rtl/top.v:3 Compile module "work@top". - -[NOTE :CP0309] rtl/top.v:7 Implicit port type (wire) for "vsync". - -[NOTE :CP0309] rtl/pong_graph.v:9 Implicit port type (wire) for "hit_left", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/vga_sync.v:4 Implicit port type (wire) for "vsync", -there are 3 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] sim/bench.v:7 Top level module "work@testbench". - -[WARNI:EL0505] rtl/front_rom.v:1 Multiply defined module "work@font_rom", - rtl/data.v:1 previous definition. - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 4. - -[NOTE :EL0510] Nb instances: 10. - -[NOTE :EL0511] Nb leaf instances: 1. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 6 -[ NOTE] : 8 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -4.07user 0.17system 0:02.03elapsed 208%CPU (0avgtext+0avgdata 121408maxresident)k -440inputs+832outputs (0major+27794minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/aes_core/YosysOldAes_diff.log b/SVIncCompil/Testcases/YosysOldTests/aes_core/YosysOldAes_diff.log deleted file mode 100644 index 70e38a5..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/aes_core/YosysOldAes_diff.log +++ /dev/null
@@ -1,81 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/aes_cipher_top.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_inv_cipher_top.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_inv_sbox.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_key_expand_128.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_rcon.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_sbox.v:60 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "aes_cipher_top". - -[WARNI:PA0205] cache/synth.v:3293 No timescale set for "aes_key_expand_128". - -[WARNI:PA0205] cache/synth.v:4743 No timescale set for "aes_rcon". - -[WARNI:PA0205] cache/synth.v:4913 No timescale set for "aes_sbox". - -[WARNI:PA0205] timescale.v:2 No timescale set for "aes_inv_cipher_top". - -[WARNI:PA0205] timescale.v:2 No timescale set for "aes_inv_sbox". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@aes_cipher_top". - -[INFO :CP0303] timescale.v:2 Compile module "work@aes_inv_sbox". - -[INFO :CP0303] timescale.v:2 Compile module "work@aes_inv_cipher_top". - -[INFO :CP0303] cache/synth.v:3293 Compile module "work@aes_key_expand_128". - -[INFO :CP0303] cache/synth.v:4913 Compile module "work@aes_sbox". - -[INFO :CP0303] cache/synth.v:4743 Compile module "work@aes_rcon". - -[NOTE :CP0309] cache/synth.v:4743 Implicit port type (wire) for "out". - -[NOTE :CP0309] cache/synth.v:4913 Implicit port type (wire) for "d". - -[NOTE :CP0309] cache/synth.v:3293 Implicit port type (wire) for "wo_3". - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:1 Top level module "work@aes_cipher_top". - -[NOTE :EL0503] timescale.v:2 Top level module "work@aes_inv_cipher_top". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 2. - -[NOTE :EL0509] Max instance depth: 3. - -[NOTE :EL0510] Nb instances: 46. - -[NOTE :EL0511] Nb leaf instances: 42. - -[ FATAL] : 0 -[ ERROR] : 6 -[WARNING] : 6 -[ NOTE] : 10 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -4.24user 0.19system 0:02.59elapsed 171%CPU (0avgtext+0avgdata 174880maxresident)k -0inputs+1112outputs (0major+41123minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/openmsp430/YosysOldOpen_diff.log b/SVIncCompil/Testcases/YosysOldTests/openmsp430/YosysOldOpen_diff.log deleted file mode 100644 index 2852358..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/openmsp430/YosysOldOpen_diff.log +++ /dev/null
@@ -1,183 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_all/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate". - -[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate". - -[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux". - -[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk". - -[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module". - -[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu". - -[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart". - -[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone". - -[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux". - -[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr". - -[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg". - -[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier". - -[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit". - -[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430". - -[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file". - -[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend". - -[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell". - -[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset". - -[WARNI:PA0205] rtl/omsp_wakeup_cell.v:44 No timescale set for "omsp_wakeup_cell". - -[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate". - -[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu". - -[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module". - -[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate". - -[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk". - -[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux". - -[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg". - -[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit". - -[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone". - -[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart". - -[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend". - -[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier". - -[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr". - -[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file". - -[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell". - -[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog". - -[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430". - -[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset". - -[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux". - -[INFO :CP0303] rtl/omsp_wakeup_cell.v:44 Compile module "work@omsp_wakeup_cell". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox". - -[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out". - -[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff", -there are 9 more instances of this message. - -[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s". - -[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y". - -[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_freeze", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out". - -[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk". - -[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din", -there are 15 more instances of this message. - -[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk", -there are 14 more instances of this message. - -[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout". - -[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out". - -[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk", -there are 24 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate". - -[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate". - -[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux". - -[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk". - -[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux". - -[NOTE :EL0503] rtl/openMSP430.v:46 Top level module "work@openMSP430". - -[NOTE :EL0503] rtl/omsp_wakeup_cell.v:44 Top level module "work@omsp_wakeup_cell". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 7. - -[NOTE :EL0509] Max instance depth: 4. - -[NOTE :EL0510] Nb instances: 23. - -[NOTE :EL0511] Nb leaf instances: 15. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 20 -[ NOTE] : 31 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -8.83user 0.16system 0:03.79elapsed 236%CPU (0avgtext+0avgdata 173368maxresident)k -0inputs+7448outputs (0major+45571minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/or1200/YosysOldOr_diff.log b/SVIncCompil/Testcases/YosysOldTests/or1200/YosysOldOr_diff.log deleted file mode 100644 index 8a7261d..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/or1200/YosysOldOr_diff.log +++ /dev/null
@@ -1,519 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_all/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CP0300] Compilation... - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1649 Compile module "work@BLOCK0". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1686 Compile module "work@BLOCK1A". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1673 Compile module "work@BLOCK2". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1660 Compile module "work@BLOCK1". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1696 Compile module "work@BLOCK2A". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2301 Compile module "work@DBLCTREE_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2326 Compile module "work@DBLCADDER_64_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:114 Compile module "work@BOOTHCODER_33_32". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1781 Compile module "work@DBLC_0_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2003 Compile module "work@DBLC_3_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1929 Compile module "work@DBLC_2_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2077 Compile module "work@DBLC_4_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:774 Compile module "work@FLIPFLOP". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:99 Compile module "work@DECODER". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2343 Compile module "work@MULTIPLIER_33_32". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1631 Compile module "work@INVBLOCK". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:751 Compile module "work@FULL_ADDER". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1706 Compile module "work@PRESTAGE_64". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:64 Compile module "work@PP_MIDDLE". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:78 Compile module "work@PP_HIGH". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1639 Compile module "work@XXOR1". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:90 Compile module "work@R_GATE". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2225 Compile module "work@XORSTAGE_64". - -[INFO :CP0303] rtl/or1200_cpu.v:54 Compile module "work@or1200_cpu". - -[INFO :CP0303] rtl/or1200_alu.v:53 Compile module "work@or1200_alu". - -[INFO :CP0303] rtl/or1200_cfgr.v:53 Compile module "work@or1200_cfgr". - -[INFO :CP0303] rtl/or1200_dc_ram.v:55 Compile module "work@or1200_dc_ram". - -[INFO :CP0303] rtl/or1200_ctrl.v:54 Compile module "work@or1200_ctrl". - -[INFO :CP0303] rtl/or1200_dmmu_top.v:58 Compile module "work@or1200_dmmu_top". - -[INFO :CP0303] rtl/or1200_du.v:58 Compile module "work@or1200_du". - -[INFO :CP0303] rtl/or1200_dc_tag.v:54 Compile module "work@or1200_dc_tag". - -[INFO :CP0303] rtl/or1200_dc_top.v:59 Compile module "work@or1200_dc_top". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:1855 Compile module "work@DBLC_1_64". - -[INFO :CP0303] rtl/or1200_fpu_arith.v:44 Compile module "work@or1200_fpu_arith". - -[INFO :CP0303] rtl/or1200_dpram.v:59 Compile module "work@or1200_dpram". - -[INFO :CP0303] rtl/or1200_dpram_256x32.v:69 Compile module "work@or1200_dpram_256x32". - -[INFO :CP0303] rtl/or1200_except.v:59 Compile module "work@or1200_except". - -[INFO :CP0303] rtl/or1200_fpu_intfloat_conv_except.v:40 Compile module "work@or1200_fpu_intfloat_conv_except". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2151 Compile module "work@DBLC_5_64". - -[INFO :CP0303] rtl/or1200_fpu.v:50 Compile module "work@or1200_fpu". - -[INFO :CP0303] rtl/or1200_fpu_post_norm_intfloat_conv.v:40 Compile module "work@or1200_fpu_post_norm_intfloat_conv". - -[INFO :CP0303] rtl/or1200_fpu_fcmp.v:38 Compile module "work@or1200_fpu_fcmp". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:764 Compile module "work@HALF_ADDER". - -[INFO :CP0303] rtl/or1200_fpu_div.v:44 Compile module "work@or1200_fpu_div". - -[INFO :CP0303] rtl/or1200_fpu_post_norm_addsub.v:44 Compile module "work@or1200_fpu_post_norm_addsub". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:53 Compile module "work@PP_LOW". - -[INFO :CP0303] rtl/or1200_fpu_pre_norm_mul.v:44 Compile module "work@or1200_fpu_pre_norm_mul". - -[INFO :CP0303] rtl/or1200_fpu_mul.v:44 Compile module "work@or1200_fpu_mul". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:793 Compile module "work@WALLACE_33_32". - -[INFO :CP0303] rtl/or1200_fpu_pre_norm_addsub.v:44 Compile module "work@or1200_fpu_pre_norm_addsub". - -[INFO :CP0303] rtl/or1200_ic_ram.v:56 Compile module "work@or1200_ic_ram". - -[INFO :CP0303] rtl/or1200_immu_tlb.v:97 Compile module "work@or1200_immu_tlb". - -[INFO :CP0303] rtl/or1200_fpu_post_norm_mul.v:44 Compile module "work@or1200_fpu_post_norm_mul". - -[INFO :CP0303] rtl/or1200_genpc.v:53 Compile module "work@or1200_genpc". - -[INFO :CP0303] rtl/or1200_mem2reg.v:89 Compile module "work@or1200_mem2reg". - -[INFO :CP0303] rtl/or1200_pm.v:74 Compile module "work@or1200_pm". - -[INFO :CP0303] rtl/or1200_freeze.v:58 Compile module "work@or1200_freeze". - -[INFO :CP0303] rtl/or1200_ic_top.v:55 Compile module "work@or1200_ic_top". - -[INFO :CP0303] rtl/or1200_rfram_generic.v:66 Compile module "work@or1200_rfram_generic". - -[INFO :CP0303] rtl/or1200_ic_tag.v:56 Compile module "work@or1200_ic_tag". - -[INFO :CP0303] rtl/or1200_iwb_biu.v:59 Compile module "work@or1200_iwb_biu". - -[INFO :CP0303] rtl/or1200_operandmuxes.v:53 Compile module "work@or1200_operandmuxes". - -[INFO :CP0303] rtl/or1200_immu_top.v:52 Compile module "work@or1200_immu_top". - -[INFO :CP0303] rtl/or1200_spram_1024x32.v:119 Compile module "work@or1200_spram_1024x32". - -[INFO :CP0303] rtl/or1200_reg2mem.v:80 Compile module "work@or1200_reg2mem". - -[INFO :CP0303] rtl/or1200_spram_2048x32.v:119 Compile module "work@or1200_spram_2048x32". - -[INFO :CP0303] rtl/or1200_mult_mac.v:59 Compile module "work@or1200_mult_mac". - -[INFO :CP0303] rtl/or1200_sb_fifo.v:65 Compile module "work@or1200_sb_fifo". - -[INFO :CP0303] rtl/or1200_spram_32_bw.v:60 Compile module "work@or1200_spram_32_bw". - -[INFO :CP0303] rtl/or1200_spram_1024x8.v:116 Compile module "work@or1200_spram_1024x8". - -[INFO :CP0303] rtl/or1200_qmem_top.v:82 Compile module "work@or1200_qmem_top". - -[INFO :CP0303] rtl/or1200_spram_64x22.v:116 Compile module "work@or1200_spram_64x22". - -[INFO :CP0303] rtl/or1200_spram_2048x8.v:116 Compile module "work@or1200_spram_2048x8". - -[INFO :CP0303] rtl/or1200_sb.v:54 Compile module "work@or1200_sb". - -[INFO :CP0303] rtl/or1200_tpram_32x32.v:109 Compile module "work@or1200_tpram_32x32". - -[INFO :CP0303] rtl/or1200_amultp2_32x32.v:2373 Compile module "work@or1200_amultp2_32x32". - -[INFO :CP0303] rtl/or1200_spram_512x20.v:122 Compile module "work@or1200_spram_512x20". - -[INFO :CP0303] rtl/or1200_spram_1024x32_bw.v:88 Compile module "work@or1200_spram_1024x32_bw". - -[INFO :CP0303] rtl/or1200_sprs.v:53 Compile module "work@or1200_sprs". - -[INFO :CP0303] rtl/or1200_dc_fsm.v:62 Compile module "work@or1200_dc_fsm". - -[INFO :CP0303] rtl/or1200_spram_2048x32_bw.v:91 Compile module "work@or1200_spram_2048x32_bw". - -[INFO :CP0303] rtl/or1200_spram_32x24.v:87 Compile module "work@or1200_spram_32x24". - -[INFO :CP0303] rtl/or1200_wb_biu.v:60 Compile module "work@or1200_wb_biu". - -[INFO :CP0303] rtl/or1200_spram_64x24.v:119 Compile module "work@or1200_spram_64x24". - -[INFO :CP0303] rtl/or1200_dmmu_tlb.v:59 Compile module "work@or1200_dmmu_tlb". - -[INFO :CP0303] rtl/or1200_tt.v:49 Compile module "work@or1200_tt". - -[INFO :CP0303] rtl/or1200_dpram_32x32.v:133 Compile module "work@or1200_dpram_32x32". - -[INFO :CP0303] rtl/or1200_fpu_addsub.v:45 Compile module "work@or1200_fpu_addsub". - -[INFO :CP0303] rtl/or1200_fpu_intfloat_conv.v:68 Compile module "work@or1200_fpu_intfloat_conv". - -[INFO :CP0303] rtl/or1200_fpu_post_norm_div.v:45 Compile module "work@or1200_fpu_post_norm_div". - -[INFO :CP0303] rtl/or1200_fpu_pre_norm_div.v:44 Compile module "work@or1200_fpu_pre_norm_div". - -[INFO :CP0303] rtl/or1200_ic_fsm.v:59 Compile module "work@or1200_ic_fsm". - -[INFO :CP0303] rtl/or1200_if.v:53 Compile module "work@or1200_if". - -[INFO :CP0303] rtl/or1200_lsu.v:55 Compile module "work@or1200_lsu". - -[INFO :CP0303] rtl/or1200_pic.v:52 Compile module "work@or1200_pic". - -[INFO :CP0303] rtl/or1200_rf.v:54 Compile module "work@or1200_rf". - -[INFO :CP0303] rtl/or1200_spram.v:59 Compile module "work@or1200_spram". - -[INFO :CP0303] rtl/or1200_spram_128x32.v:83 Compile module "work@or1200_spram_128x32". - -[INFO :CP0303] rtl/or1200_spram_256x21.v:125 Compile module "work@or1200_spram_256x21". - -[INFO :CP0303] rtl/or1200_spram_64x14.v:116 Compile module "work@or1200_spram_64x14". - -[INFO :CP0303] rtl/or1200_top.v:56 Compile module "work@or1200_top". - -[INFO :CP0303] rtl/or1200_wbmux.v:53 Compile module "work@or1200_wbmux". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process". - -[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1649 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1696 Implicit port type (wire) for "GOUT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1781 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2077 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:751 Implicit port type (wire) for "SAVE", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:78 Implicit port type (wire) for "PPBIT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:90 Implicit port type (wire) for "PPBIT". - -[NOTE :CP0309] rtl/or1200_ctrl.v:60 Implicit port type (wire) for "if_flushpipe", -there are 23 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dc_top.v:64 Implicit port type (wire) for "dcsb_dat_o", -there are 12 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dpram_256x32.v:71 Implicit port type (wire) for "do_a". - -[NOTE :CP0309] rtl/or1200_fpu.v:55 Implicit port type (wire) for "result", -there are 6 more instances of this message. - -[NOTE :CP0309] rtl/or1200_fpu_fcmp.v:38 Implicit port type (wire) for "unordered", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/or1200_genpc.v:58 Implicit port type (wire) for "icpu_adr_o", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/or1200_ic_top.v:60 Implicit port type (wire) for "icbiu_dat_o", -there are 11 more instances of this message. - -[NOTE :CP0309] rtl/or1200_reg2mem.v:80 Implicit port type (wire) for "memdata". - -[NOTE :CP0309] rtl/or1200_spram_1024x8.v:118 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_2048x8.v:118 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_512x20.v:124 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_sprs.v:58 Implicit port type (wire) for "flag", -there are 13 more instances of this message. - -[NOTE :CP0309] rtl/or1200_wb_biu.v:71 Implicit port type (wire) for "biu_dat_o", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1660 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:114 Implicit port type (wire) for "SUMMAND". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1855 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2151 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:764 Implicit port type (wire) for "SAVE", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:53 Implicit port type (wire) for "PPBIT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:793 Implicit port type (wire) for "CARRY", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2373 Implicit port type (wire) for "P". - -[NOTE :CP0309] rtl/or1200_dc_fsm.v:70 Implicit port type (wire) for "dcram_we", -there are 13 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dmmu_tlb.v:64 Implicit port type (wire) for "hit", -there are 7 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dpram_32x32.v:135 Implicit port type (wire) for "do_a". - -[NOTE :CP0309] rtl/or1200_fpu_intfloat_conv.v:70 Implicit port type (wire) for "inv", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/or1200_fpu_pre_norm_div.v:50 Implicit port type (wire) for "dvdnd_50_o", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_ic_fsm.v:67 Implicit port type (wire) for "saved_addr", -there are 7 more instances of this message. - -[NOTE :CP0309] rtl/or1200_if.v:61 Implicit port type (wire) for "if_insn", -there are 7 more instances of this message. - -[NOTE :CP0309] rtl/or1200_lsu.v:61 Implicit port type (wire) for "lsu_dataout", -there are 10 more instances of this message. - -[NOTE :CP0309] rtl/or1200_pic.v:55 Implicit port type (wire) for "pic_wakeup", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_rf.v:59 Implicit port type (wire) for "cy_we_o", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/or1200_spram.v:62 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_128x32.v:85 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_256x21.v:127 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_64x14.v:118 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_top.v:62 Implicit port type (wire) for "iwb_cyc_o", -there are 30 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1686 Implicit port type (wire) for "GOUT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2326 Implicit port type (wire) for "SUM", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1929 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:99 Implicit port type (wire) for "TWOPOS", -there are 3 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1631 Implicit port type (wire) for "GOUT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:64 Implicit port type (wire) for "PPBIT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2225 Implicit port type (wire) for "SUM", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dc_ram.v:61 Implicit port type (wire) for "dataout". - -[NOTE :CP0309] rtl/or1200_dmmu_top.v:64 Implicit port type (wire) for "dcpu_tag_o", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/or1200_du.v:65 Implicit port type (wire) for "du_dsr", -there are 10 more instances of this message. - -[NOTE :CP0309] rtl/or1200_fpu_post_norm_intfloat_conv.v:43 Implicit port type (wire) for "out", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/or1200_fpu_pre_norm_mul.v:49 Implicit port type (wire) for "fracta_24_o", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_ic_ram.v:62 Implicit port type (wire) for "dataout". - -[NOTE :CP0309] rtl/or1200_immu_tlb.v:102 Implicit port type (wire) for "hit", -there are 5 more instances of this message. - -[NOTE :CP0309] rtl/or1200_pm.v:76 Implicit port type (wire) for "spr_dat_o", -there are 9 more instances of this message. - -[NOTE :CP0309] rtl/or1200_spram_1024x32.v:121 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_2048x32.v:121 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_32_bw.v:63 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_64x22.v:118 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_tpram_32x32.v:111 Implicit port type (wire) for "do_a", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1673 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2301 Implicit port type (wire) for "GOUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:2003 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:774 Implicit port type (wire) for "DOUT". - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1706 Implicit port type (wire) for "POUT", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_amultp2_32x32.v:1639 Implicit port type (wire) for "SUM". - -[NOTE :CP0309] rtl/or1200_cpu.v:59 Implicit port type (wire) for "ic_en", -there are 41 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dc_tag.v:60 Implicit port type (wire) for "tag_v", -there are 2 more instances of this message. - -[NOTE :CP0309] rtl/or1200_dpram.v:62 Implicit port type (wire) for "do_a". - -[NOTE :CP0309] rtl/or1200_except.v:69 Implicit port type (wire) for "except_flushpipe", -there are 8 more instances of this message. - -[NOTE :CP0309] rtl/or1200_fpu_div.v:52 Implicit port type (wire) for "ready_o", -there are 4 more instances of this message. - -[NOTE :CP0309] rtl/or1200_freeze.v:67 Implicit port type (wire) for "genpc_freeze", -there are 4 more instances of this message. - -[NOTE :CP0309] rtl/or1200_ic_tag.v:62 Implicit port type (wire) for "tag_v", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_immu_top.v:58 Implicit port type (wire) for "icpu_tag_o", -there are 6 more instances of this message. - -[NOTE :CP0309] rtl/or1200_mult_mac.v:65 Implicit port type (wire) for "mult_mac_stall", -there are 1 more instances of this message. - -[NOTE :CP0309] rtl/or1200_qmem_top.v:93 Implicit port type (wire) for "qmemicpu_dat_o", -there are 21 more instances of this message. - -[NOTE :CP0309] rtl/or1200_sb.v:63 Implicit port type (wire) for "dcsb_dat_o", -there are 9 more instances of this message. - -[NOTE :CP0309] rtl/or1200_spram_1024x32_bw.v:90 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_2048x32_bw.v:93 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_32x24.v:89 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_spram_64x24.v:121 Implicit port type (wire) for "doq". - -[NOTE :CP0309] rtl/or1200_tt.v:53 Implicit port type (wire) for "intr". - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] rtl/or1200_dc_ram.v:55 Top level module "work@or1200_dc_ram". - -[NOTE :EL0503] rtl/or1200_dpram_256x32.v:69 Top level module "work@or1200_dpram_256x32". - -[NOTE :EL0503] rtl/or1200_dc_tag.v:54 Top level module "work@or1200_dc_tag". - -[NOTE :EL0503] rtl/or1200_dc_fsm.v:62 Top level module "work@or1200_dc_fsm". - -[NOTE :EL0503] rtl/or1200_dpram_32x32.v:133 Top level module "work@or1200_dpram_32x32". - -[NOTE :EL0503] rtl/or1200_spram_1024x32.v:119 Top level module "work@or1200_spram_1024x32". - -[NOTE :EL0503] rtl/or1200_spram_2048x32.v:119 Top level module "work@or1200_spram_2048x32". - -[NOTE :EL0503] rtl/or1200_spram_32_bw.v:60 Top level module "work@or1200_spram_32_bw". - -[NOTE :EL0503] rtl/or1200_spram_64x22.v:116 Top level module "work@or1200_spram_64x22". - -[NOTE :EL0503] rtl/or1200_top.v:56 Top level module "work@or1200_top". - -[NOTE :EL0503] rtl/or1200_fpu_arith.v:44 Top level module "work@or1200_fpu_arith". - -[NOTE :EL0503] rtl/or1200_sb_fifo.v:65 Top level module "work@or1200_sb_fifo". - -[NOTE :EL0503] rtl/or1200_spram_128x32.v:83 Top level module "work@or1200_spram_128x32". - -[NOTE :EL0503] rtl/or1200_fpu_fcmp.v:38 Top level module "work@or1200_fpu_fcmp". - -[NOTE :EL0503] rtl/or1200_spram_2048x8.v:116 Top level module "work@or1200_spram_2048x8". - -[NOTE :EL0503] rtl/or1200_spram_512x20.v:122 Top level module "work@or1200_spram_512x20". - -[NOTE :EL0503] rtl/or1200_rfram_generic.v:66 Top level module "work@or1200_rfram_generic". - -[NOTE :EL0503] rtl/or1200_spram_1024x32_bw.v:88 Top level module "work@or1200_spram_1024x32_bw". - -[NOTE :EL0503] rtl/or1200_spram_2048x32_bw.v:91 Top level module "work@or1200_spram_2048x32_bw". - -[NOTE :EL0503] rtl/or1200_spram_32x24.v:87 Top level module "work@or1200_spram_32x24". - -[NOTE :EL0503] rtl/or1200_spram_64x24.v:119 Top level module "work@or1200_spram_64x24". - -[NOTE :EL0503] rtl/or1200_tpram_32x32.v:109 Top level module "work@or1200_tpram_32x32". - -[NOTE :EL0503] rtl/or1200_fpu_intfloat_conv.v:68 Top level module "work@or1200_fpu_intfloat_conv". - -[NOTE :EL0503] rtl/or1200_iwb_biu.v:59 Top level module "work@or1200_iwb_biu". - -[NOTE :EL0503] rtl/or1200_spram_1024x8.v:116 Top level module "work@or1200_spram_1024x8". - -[NOTE :EL0503] rtl/or1200_spram_256x21.v:125 Top level module "work@or1200_spram_256x21". - -[NOTE :EL0503] rtl/or1200_spram_64x14.v:116 Top level module "work@or1200_spram_64x14". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 27. - -[NOTE :EL0509] Max instance depth: 9. - -[NOTE :EL0510] Nb instances: 1884. - -[NOTE :EL0511] Nb leaf instances: 1635. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 0 -[ NOTE] : 117 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -14.40user 0.36system 0:06.28elapsed 234%CPU (0avgtext+0avgdata 497696maxresident)k -0inputs+41584outputs (0major+126754minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/sasc/YosysOldSasc_diff.log b/SVIncCompil/Testcases/YosysOldTests/sasc/YosysOldSasc_diff.log deleted file mode 100644 index 5768de1..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/sasc/YosysOldSasc_diff.log +++ /dev/null
@@ -1,63 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/sasc_brg.v:66 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/sasc_fifo4.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/sasc_top.v:62 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "sasc_fifo4". - -[WARNI:PA0205] cache/synth.v:282 No timescale set for "sasc_top". - -[WARNI:PA0205] timescale.v:22 No timescale set for "sasc_brg". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] timescale.v:22 Compile module "work@sasc_brg". - -[INFO :CP0303] cache/synth.v:1 Compile module "work@sasc_fifo4". - -[INFO :CP0303] cache/synth.v:282 Compile module "work@sasc_top". - -[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout", -there are 2 more instances of this message. - -[NOTE :CP0309] cache/synth.v:282 Implicit port type (wire) for "dout_o", -there are 2 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:282 Top level module "work@sasc_top". - -[NOTE :EL0503] timescale.v:22 Top level module "work@sasc_brg". - -[NOTE :EL0504] Multiple top level modules in design. - -[NOTE :EL0508] Nb Top level modules: 2. - -[NOTE :EL0509] Max instance depth: 2. - -[NOTE :EL0510] Nb instances: 4. - -[NOTE :EL0511] Nb leaf instances: 3. - -[ FATAL] : 0 -[ ERROR] : 3 -[WARNING] : 3 -[ NOTE] : 9 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.42user 0.06system 0:01.56elapsed 223%CPU (0avgtext+0avgdata 63028maxresident)k -96inputs+152outputs (0major+13064minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/simple_spi/YosysOldSimpleSpi_diff.log b/SVIncCompil/Testcases/YosysOldTests/simple_spi/YosysOldSimpleSpi_diff.log deleted file mode 100644 index c88e6a4..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/simple_spi/YosysOldSimpleSpi_diff.log +++ /dev/null
@@ -1,69 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/fifo4.v:57 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/simple_spi_top.v:74 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "$paramod\fifo4\dw=8". - -[WARNI:PA0205] cache/synth.v:282 No timescale set for "simple_spi_top". - -[WARNI:PA0205] timescale.v:5 No timescale set for "fifo4". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@$paramod\fifo4\dw=8". - -[INFO :CP0303] timescale.v:5 Compile module "work@fifo4". - -[INFO :CP0303] cache/synth.v:282 Compile module "work@simple_spi_top". - -[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout", -there are 2 more instances of this message. - -[NOTE :CP0309] timescale.v:5 Implicit port type (wire) for "dout", -there are 2 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:1 Top level module "work@$paramod\fifo4\dw=8". - -[NOTE :EL0503] cache/synth.v:282 Top level module "work@simple_spi_top". - -[NOTE :EL0504] Multiple top level modules in design. - -[WARNI:EL0500] cache/synth.v:1191 Cannot find a module definition for "work@simple_spi_top::$paramod\fifo4\dw=8 ". - -[WARNI:EL0500] cache/synth.v:1202 Cannot find a module definition for "work@simple_spi_top::$paramod\fifo4\dw=8 ". - -[NOTE :EL0508] Nb Top level modules: 2. - -[NOTE :EL0509] Max instance depth: 2. - -[NOTE :EL0510] Nb instances: 4. - -[NOTE :EL0511] Nb leaf instances: 3. - -[WARNI:EL0512] Nb undefined modules: 1. - -[WARNI:EL0513] Nb undefined instances: 2. - -[ FATAL] : 0 -[ ERROR] : 2 -[WARNING] : 7 -[ NOTE] : 9 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.42user 0.05system 0:01.35elapsed 256%CPU (0avgtext+0avgdata 72224maxresident)k -152inputs+184outputs (3major+15368minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/spi/YosysOldSpi_diff.log b/SVIncCompil/Testcases/YosysOldTests/spi/YosysOldSpi_diff.log deleted file mode 100644 index 06526fd..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/spi/YosysOldSpi_diff.log +++ /dev/null
@@ -1,277 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/spi_clgen.v:41 Cannot open include file "spi_defines.v". - -[ERROR:PP0101] rtl/spi_clgen.v:42 Cannot open include file "timescale.v". - -[ERROR:PP0102] rtl/spi_clgen.v:53 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_clgen.v:62 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_clgen.v:67 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_clgen.v:68 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_clgen.v:74 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_clgen.v:80 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0101] rtl/spi_shift.v:41 Cannot open include file "spi_defines.v". - -[ERROR:PP0101] rtl/spi_shift.v:42 Cannot open include file "timescale.v". - -[ERROR:PP0102] rtl/spi_shift.v:55 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:65 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PP0102] rtl/spi_shift.v:73 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:74 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PP0102] rtl/spi_shift.v:75 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:76 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:82 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:83 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:84 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:95 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:99 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:101 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:122 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_shift.v:129 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PP0102] rtl/spi_shift.v:234 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0101] rtl/spi_top.v:42 Cannot open include file "spi_defines.v". - -[ERROR:PP0101] rtl/spi_top.v:43 Cannot open include file "timescale.v". - -[ERROR:PP0102] rtl/spi_top.v:72 Unknown macro "SPI_SS_NB". - -[ERROR:PP0102] rtl/spi_top.v:82 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_top.v:83 Unknown macro "SPI_CTRL_BIT_NB". - -[ERROR:PP0102] rtl/spi_top.v:84 Unknown macro "SPI_SS_NB". - -[ERROR:PP0102] rtl/spi_top.v:86 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PP0102] rtl/spi_top.v:89 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_DEVIDE". - -[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_CTRL". - -[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_TX_0". - -[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_TX_1". - -[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_TX_2". - -[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_TX_3". - -[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_SS". - -[ERROR:PP0102] rtl/spi_top.v:115 Unknown macro "SPI_OFS_BITS". - -[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_RX_0". - -[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PP0102] rtl/spi_top.v:129 Unknown macro "SPI_RX_1". - -[ERROR:PP0102] rtl/spi_top.v:130 Unknown macro "SPI_RX_2". - -[ERROR:PP0102] rtl/spi_top.v:131 Unknown macro "SPI_RX_3". - -[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL". - -[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL_BIT_NB". - -[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DEVIDE". - -[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS". - -[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS_NB". - -[ERROR:PP0102] rtl/spi_top.v:177 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PP0102] rtl/spi_top.v:215 Unknown macro "SPI_CTRL_BIT_NB". - -[ERROR:PP0102] rtl/spi_top.v:221 Unknown macro "SPI_CTRL_BIT_NB". - -[ERROR:PP0102] rtl/spi_top.v:224 Unknown macro "SPI_CTRL_GO". - -[ERROR:PP0102] rtl/spi_top.v:227 Unknown macro "SPI_CTRL_RX_NEGEDGE". - -[ERROR:PP0102] rtl/spi_top.v:228 Unknown macro "SPI_CTRL_TX_NEGEDGE". - -[ERROR:PP0102] rtl/spi_top.v:229 Unknown macro "SPI_CTRL_GO". - -[ERROR:PP0102] rtl/spi_top.v:230 Unknown macro "SPI_CTRL_CHAR_LEN". - -[ERROR:PP0102] rtl/spi_top.v:231 Unknown macro "SPI_CTRL_LSB". - -[ERROR:PP0102] rtl/spi_top.v:232 Unknown macro "SPI_CTRL_IE". - -[ERROR:PP0102] rtl/spi_top.v:233 Unknown macro "SPI_CTRL_ASS". - -[ERROR:PP0102] rtl/spi_top.v:239 Unknown macro "SPI_SS_NB". - -[ERROR:PP0102] rtl/spi_top.v:273 Unknown macro "SPI_SS_NB". - -[ERROR:PP0102] rtl/spi_top.v:279 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0207] timescale.v:11 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!!', - input [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!! -1:0] divider; // clock divider (output clock is divided by this value) - ^-- ./slpp_unit/work/rtl/spi_clgen.v:51 col:13. - -[ERROR:PA0203] timescale.v:11 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0203] timescale.v:25 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0203] timescale.v:26 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0203] timescale.v:32 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0203] timescale.v:38 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0207] timescale.v:13 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!!', - input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!! -1:0] len; // data len in bits (minus one) - ^-- ./slpp_unit/work/rtl/spi_shift.v:53 col:9. - -[ERROR:PA0203] timescale.v:13 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:40 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:41 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:42 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:53 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:57 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:59 Unknown macro "SPI_CHAR_LEN_BITS". - -[ERROR:PA0203] timescale.v:87 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PA0207] timescale.v:29 Syntax error: no viable alternative at input 'output [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!!', - output [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!! -1:0] ss_pad_o; // slave select - ^-- ./slpp_unit/work/rtl/spi_top.v:70 col:19. - -[ERROR:PA0203] timescale.v:29 Unknown macro "SPI_SS_NB". - -[ERROR:PA0203] timescale.v:61 Unknown macro "SPI_DEVIDE". - -[ERROR:PA0203] timescale.v:62 Unknown macro "SPI_CTRL". - -[ERROR:PA0203] timescale.v:63 Unknown macro "SPI_TX_0". - -[ERROR:PA0203] timescale.v:64 Unknown macro "SPI_TX_1". - -[ERROR:PA0203] timescale.v:65 Unknown macro "SPI_TX_2". - -[ERROR:PA0203] timescale.v:66 Unknown macro "SPI_TX_3". - -[ERROR:PA0203] timescale.v:67 Unknown macro "SPI_SS". - -[ERROR:PA0203] timescale.v:73 Unknown macro "SPI_RX_0". - -[ERROR:PA0203] timescale.v:73 Unknown macro "SPI_MAX_CHAR". - -[ERROR:PA0203] timescale.v:74 Unknown macro "SPI_RX_1". - -[ERROR:PA0203] timescale.v:75 Unknown macro "SPI_RX_2". - -[ERROR:PA0203] timescale.v:76 Unknown macro "SPI_RX_3". - -[ERROR:PA0203] timescale.v:77 Unknown macro "SPI_CTRL". - -[ERROR:PA0203] timescale.v:78 Unknown macro "SPI_DEVIDE". - -[ERROR:PA0203] timescale.v:79 Unknown macro "SPI_SS". - -[ERROR:PA0203] timescale.v:120 Unknown macro "SPI_DIVIDER_LEN". - -[ERROR:PA0203] timescale.v:130 Unknown macro "SPI_CTRL_BIT_NB". - -[ERROR:PA0203] timescale.v:154 Unknown macro "SPI_SS_NB". - -[ERROR:PA0203] timescale.v:160 Unknown macro "SPI_SS_NB". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "spi_clgen". - -[WARNI:PA0205] cache/synth.v:359 No timescale set for "spi_shift". - -[WARNI:PA0205] cache/synth.v:4166 No timescale set for "spi_top". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@spi_clgen". - -[INFO :CP0303] cache/synth.v:359 Compile module "work@spi_shift". - -[INFO :CP0303] cache/synth.v:4166 Compile module "work@spi_top". - -[NOTE :CP0309] cache/synth.v:359 Implicit port type (wire) for "last", -there are 1 more instances of this message. - -[NOTE :CP0309] cache/synth.v:4166 Implicit port type (wire) for "wb_err_o", -there are 3 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:4166 Top level module "work@spi_top". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 2. - -[NOTE :EL0510] Nb instances: 3. - -[NOTE :EL0511] Nb leaf instances: 2. - -[ FATAL] : 0 -[ ERROR] : 109 -[WARNING] : 3 -[ NOTE] : 7 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.80user 0.14system 0:01.67elapsed 235%CPU (0avgtext+0avgdata 121756maxresident)k -392inputs+704outputs (0major+27740minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/ss_pcm/YosysOldSsPcm_diff.log b/SVIncCompil/Testcases/YosysOldTests/ss_pcm/YosysOldSsPcm_diff.log deleted file mode 100644 index 9c8f6ea..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/ss_pcm/YosysOldSsPcm_diff.log +++ /dev/null
@@ -1,46 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/pcm_slv_top.v:65 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "pcm_slv_top". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@pcm_slv_top". - -[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout_o". - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:1 Top level module "work@pcm_slv_top". - -[WARNI:EL0505] timescale.v:11 Multiply defined module "work@pcm_slv_top", - cache/synth.v:1 previous definition. - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 1. - -[NOTE :EL0510] Nb instances: 1. - -[NOTE :EL0511] Nb leaf instances: 1. - -[ FATAL] : 0 -[ ERROR] : 1 -[WARNING] : 2 -[ NOTE] : 6 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -1.26user 0.03system 0:00.88elapsed 145%CPU (0avgtext+0avgdata 49140maxresident)k -0inputs+112outputs (0major+9569minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/systemcaes/YosysOldSystem_diff.log b/SVIncCompil/Testcases/YosysOldTests/systemcaes/YosysOldSystem_diff.log deleted file mode 100644 index 1619f2a..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/systemcaes/YosysOldSystem_diff.log +++ /dev/null
@@ -1,79 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "aes". - -[WARNI:PA0205] cache/synth.v:6759 No timescale set for "byte_mixcolum". - -[WARNI:PA0205] cache/synth.v:6906 No timescale set for "keysched". - -[WARNI:PA0205] cache/synth.v:9037 No timescale set for "mixcolum". - -[WARNI:PA0205] cache/synth.v:12017 No timescale set for "sbox". - -[WARNI:PA0205] cache/synth.v:12581 No timescale set for "subbytes". - -[WARNI:PA0205] cache/synth.v:15275 No timescale set for "word_mixcolum". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@aes". - -[INFO :CP0303] cache/synth.v:6906 Compile module "work@keysched". - -[INFO :CP0303] cache/synth.v:6759 Compile module "work@byte_mixcolum". - -[INFO :CP0303] cache/synth.v:9037 Compile module "work@mixcolum". - -[INFO :CP0303] cache/synth.v:12581 Compile module "work@subbytes". - -[INFO :CP0303] cache/synth.v:15275 Compile module "work@word_mixcolum". - -[INFO :CP0303] cache/synth.v:12017 Compile module "work@sbox". - -[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "data_o". - -[NOTE :CP0309] cache/synth.v:12017 Implicit port type (wire) for "data_o". - -[NOTE :CP0309] cache/synth.v:6759 Implicit port type (wire) for "outx", -there are 1 more instances of this message. - -[NOTE :CP0309] cache/synth.v:12581 Implicit port type (wire) for "sbox_data_o", -there are 1 more instances of this message. - -[NOTE :CP0309] cache/synth.v:6906 Implicit port type (wire) for "new_key_o", -there are 3 more instances of this message. - -[NOTE :CP0309] cache/synth.v:15275 Implicit port type (wire) for "outx", -there are 1 more instances of this message. - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:1 Top level module "work@aes". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 4. - -[NOTE :EL0510] Nb instances: 10. - -[NOTE :EL0511] Nb leaf instances: 7. - -[ FATAL] : 0 -[ ERROR] : 0 -[WARNING] : 7 -[ NOTE] : 11 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -5.79user 0.26system 0:02.84elapsed 213%CPU (0avgtext+0avgdata 252472maxresident)k -1080inputs+2056outputs (0major+60482minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/YosysOldTests/usb_phy/YosysOldUsb_diff.log b/SVIncCompil/Testcases/YosysOldTests/usb_phy/YosysOldUsb_diff.log deleted file mode 100644 index 60d10dd..0000000 --- a/SVIncCompil/Testcases/YosysOldTests/usb_phy/YosysOldUsb_diff.log +++ /dev/null
@@ -1,58 +0,0 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. - -[INFO :CM0024] Executing with 4 threads. - -[INFO :CM0020] Separate compilation-unit mode is on. - -[ERROR:PP0101] rtl/usb_phy.v:75 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/usb_rx_phy.v:77 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/usb_tx_phy.v:75 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "usb_phy". - -[WARNI:PA0205] cache/synth.v:109 No timescale set for "usb_rx_phy". - -[WARNI:PA0205] cache/synth.v:645 No timescale set for "usb_tx_phy". - -[INFO :CP0300] Compilation... - -[INFO :CP0303] cache/synth.v:1 Compile module "work@usb_phy". - -[INFO :CP0303] cache/synth.v:645 Compile module "work@usb_tx_phy". - -[INFO :CP0303] cache/synth.v:109 Compile module "work@usb_rx_phy". - -[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "txdp", -there are 8 more instances of this message. - -[NOTE :CP0309] cache/synth.v:109 Implicit port type (wire) for "RxError_o". - -[INFO :EL0526] Design Elaboration... - -[NOTE :EL0503] cache/synth.v:1 Top level module "work@usb_phy". - -[NOTE :EL0508] Nb Top level modules: 1. - -[NOTE :EL0509] Max instance depth: 2. - -[NOTE :EL0510] Nb instances: 3. - -[NOTE :EL0511] Nb leaf instances: 2. - -[ FATAL] : 0 -[ ERROR] : 3 -[WARNING] : 3 -[ NOTE] : 7 - -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.56user 0.04system 0:01.43elapsed 252%CPU (0avgtext+0avgdata 71676maxresident)k -128inputs+208outputs (0major+15309minor)pagefaults 0swaps