| commit | e2529f92cedbbcb87ff4328ff53705669050198d | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Fri Nov 15 11:39:00 2019 -0800 |
| committer | GitHub <noreply@github.com> | Fri Nov 15 11:39:00 2019 -0800 |
| tree | 000072008a772106e7c4e035423ca0f7ecc83413 | |
| parent | 14189593b2851f86e27e0604e4a37a0d9629aa5c [diff] | |
| parent | 1c596881d1a7fc4baa7972b1f16b2e3d461aa200 [diff] |
Merge pull request #51 from hzeller/no-const-on-integral-return-type Don't use const for integral return types. It is confusing and doesn't
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.