blob: 6026810be93c6ba2261bc8ff1fd35bfaa513b0ac [file] [log] [blame]
VPD2VCD ?= vpd2vcd
PYTHON ?= python
TRACEDIFF ?= $(BP_COMMON_DIR)/software/tracediff.py
UNHARDWARE_DIR ?= $(BP_EXTERNAL_DIR)/agile-unhardware
UNHARDWARE_MODEL ?= blackparrot
## Tool specific options
VCS_OPTIONS ?= +vcs+finish+5000000000ps # Change this to run longer / shorter
VCS_OPTIONS += +vcs+lic+wait # Wait for license
VCS_OPTIONS += +libext+.v+.vlib+.vh # Find library files with these extensions
VCS_OPTIONS += +vcs+loopdetect +vcs+loopreport
VCS_BUILD_OPTS += -full64 # Compile a 64-bit executable
VCS_BUILD_OPTS += -sverilog # Enable SystemVerilog
VCS_BUILD_OPTS += -timescale=1ps/1ps # Set timescale
VCS_BUILD_OPTS += -assert svaext # Enable elaboration system tasks
VCS_BUILD_OPTS += -CFLAGS "-I$(BP_EXTERNAL_DIR)/include -std=c++11"
VCS_BUILD_OPTS += -LDFLAGS "-L$(BP_EXTERNAL_DIR)/lib -ldramsim -Wl,-rpath=$(BP_EXTERNAL_DIR)/lib"
VCS_BUILD_OPTS += +lint=TFIPC-L
VCS_BUILD_OPTS += -notice
LINT_OPTIONS = +lint=all,noSVA-UA,noSVA-NSVU,noNS,noVCDE
DUMP ?= 0
COV ?= 0
ifeq ($(DUMP), 1)
VCS_BUILD_OPTS += -debug_all
VCS_OPTIONS += +vcs+vcdpluson # Enable vcd dump
VCS_OPTIONS += +memcbk # Dump memory
endif
ifeq ($(COV), 1)
VCS_OPTIONS += -cm line+tgl
VCS_OPTIONS += -cm_dir $(COV_DIR)/$(PROG)
VCS_BUILD_OPTS += -cm_hier $(SYN_PATH)/coverage_hier.vcs
VCS_BUILD_OPTS += -cm_line contassign
VCS_BUILD_OPTS += -cm_noconst
VCS_BUILD_OPTS += -cm_seqnoconst
URG_OPTIONS = -full64
URG_OPTIONS += -show tests
URG_OPTIONS += -dir $(COV_DIR)/*
URG_OPTIONS += -format both
URG_OPTIONS += -dbname coverage
endif
.PHONY: deps.v lint.v build.v run.v sim.v clean.v
# Alias run.v to sim.v
run.v: sim.v
dirs.v:
$(eval RESULTS_DIR := $(RESULTS_PATH)/vcs)
$(eval REPORT_DIR := $(REPORT_PATH)/vcs)
$(eval SIM_DIR := $(RESULTS_DIR)/$(TB).$(CFG).sim/$(PROG))
$(eval BUILD_DIR := $(RESULTS_DIR)/$(TB).$(CFG).build)
$(eval COV_DIR := $(RESULTS_DIR)/$(TB).$(CFG).cov)
$(eval LOG_DIR := $(LOG_PATH)/vcs)
$(shell mkdir -p $(LOG_DIR))
$(shell mkdir -p $(REPORT_DIR))
lint.v: VCS_BUILD_OPTS += $(LINT_OPTIONS)
lint.v: override BUILD_LOG = $(LOG_DIR)/$(TB).$(CFG).lint.log
lint.v: override BUILD_REPORT = $(REPORT_DIR)/$(TB).$(CFG).lint.rpt
lint.v: override BUILD_ERROR = $(REPORT_DIR)/$(TB).$(CFG).lint.err
lint.v: build.v
BUILD_LOG ?= $(LOG_DIR)/$(TB).$(CFG).build.log
BUILD_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).build.rpt
BUILD_ERROR ?= $(REPORT_DIR)/$(TB).$(CFG).build.err
pre-build.v: dirs.v
$(shell mkdir -p $(BUILD_DIR))
$(eval include $(TB_PATH)/$(TB)/Makefile.frag)
-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/testbench.v > $(BUILD_DIR)/testbench.v
-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/wrapper.v > $(BUILD_DIR)/wrapper.v
-@cp $(TB_PATH)/$(TB)/test_bp.v $(BUILD_DIR)/test_bp.v
-@grep -v -e "^\#" $(SYN_PATH)/flist.vcs > $(BUILD_DIR)/flist.vcs
-@grep -v -e "^\#" $(TB_PATH)/$(TB)/flist.vcs >> $(BUILD_DIR)/flist.vcs
-@echo $(BUILD_DIR)/wrapper.v >> $(BUILD_DIR)/flist.vcs
-@echo $(BUILD_DIR)/testbench.v >> $(BUILD_DIR)/flist.vcs
-@echo $(BUILD_DIR)/test_bp.v >> $(BUILD_DIR)/flist.vcs
build.v: pre-build.v
-cd $(BUILD_DIR); $(VCS) $(VCS_OPTIONS) $(VCS_BUILD_OPTS) $(HDL_PARAMS) -top test_bp -f flist.vcs -o simv \
| tee $(BUILD_LOG)
-@grep "Error" -A 5 $(BUILD_LOG) > $(BUILD_ERROR);
-@tail -n 2 $(BUILD_LOG) > $(BUILD_REPORT)
-@test -s $(BUILD_ERROR) && echo "FAILED" >> $(BUILD_REPORT) \
|| rm $(BUILD_ERROR)
sim.v: SIM_LOG ?= $(LOG_DIR)/$(TB).$(CFG).sim.$(PROG).log
sim.v: SIM_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).sim.$(PROG).rpt
sim.v: SIM_ERROR ?= $(REPORT_DIR)/$(TB).$(CFG).sim.$(PROG).err
sim.v: PROG ?= rv64ui-p-simple
sim.v: dirs.v
$(shell mkdir -p $(SIM_DIR))
-@ln -sf $(BUILD_DIR)/simv $(SIM_DIR)/simv
-@ln -sf $(BUILD_DIR)/simv.daidir $(SIM_DIR)/simv.daidir
-@cp $(MEM_PATH)/$(PROG).mem $(SIM_DIR)/prog.mem
-@cp $(MEM_PATH)/$(PROG).riscv $(SIM_DIR)/prog.elf
-@cp $(MEM_PATH)/$(PROG).dump $(SIM_DIR)/prog.dump
-@cp $(MEM_PATH)/$(PROG).spike $(SIM_DIR)/commit.spike
-@cp $(BP_COMMON_DIR)/test/cfg/$(DRAMSIM_CH_CFG) $(SIM_DIR)/dram_ch.ini
-@cp $(BP_COMMON_DIR)/test/cfg/$(DRAMSIM_SYS_CFG) $(SIM_DIR)/dram_sys.ini
-@cp $(CCE_MEM_PATH)/$(CCE_MEM) $(SIM_DIR)/cce_ucode.mem
-cd $(SIM_DIR); ./simv $(VCS_OPTIONS) | tee $(SIM_LOG)
-@grep "PASS" $(SIM_LOG) || echo "FAILED" > $(SIM_ERROR)
-@grep "PASS" -A 9 $(SIM_LOG) > $(SIM_REPORT)
match.v: MATCH_LOG ?= $(LOG_DIR)/$(TB).$(CFG).match.$(PROG).log
match.v: MATCH_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).match.$(PROG).rpt
match.v: MATCH_ERROR ?= $(REPORT_DIR)/$(TB).$(CFG).match.$(PROG).err
match.v: PROG ?= rv64ui-p-simple
match.v: dirs.v
-cd $(SIM_DIR); $(PYTHON) $(TRACEDIFF) commit.spike commit.trace $(START_PC) --tolerance=$(TOLERANCE) \
| tee -a $(MATCH_LOG)
-@grep "MATCH" $(MATCH_LOG) || echo "MISMATCHED" >> $(MATCH_ERROR)
-@grep "MATCH" -A 4 $(MATCH_LOG) > $(MATCH_REPORT)
regress_riscv.v: $(RV64_REGRESSION_V)
$(RV64_REGRESSION_V):
$(MAKE) sim.v PROG=$(basename $@)
$(COREMARK_REGRESSION_V):
$(MAKE) sim.v PROG=$(basename $@)
regress_beebs.v: $(BEEBS_REGRESSION_V)
$(BEEBS_REGRESSION_V):
$(MAKE) sim.v PROG=$(basename $@)
$(MC_REGRESSION_V):
$(MAKE) sim.v CFG=$(CFG) PROG=$(basename $@)
cov.v: COV_LOG ?= $(LOG_DIR)/$(TB).$(CFG).cov.log
cov.v: COV_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).cov
cov.v: COV_HREPORT ?= $(REPORT_DIR)/$(TB).$(CFG).cov.hier.rpt
cov.v: COV_TREPORT ?= $(REPORT_DIR)/$(TB).$(CFG).cov.test.rpt
cov.v: COV_ERROR ?= $(REPORT_DIR)/$(TB).$(CFG).cov.err
cov.v: dirs.v
$(shell mkdir -p $(COV_DIR))
cd $(COV_DIR); $(URG) $(URG_OPTIONS) -log $(COV_LOG) -report $(COV_REPORT)
@cp $(COV_REPORT)/tests.txt $(COV_TREPORT)
@cp $(COV_REPORT)/hierarchy.txt $(COV_HREPORT)
wave.v: dirs.v
cd $(SIM_DIR); $(_DVE) -full64 -vpd vcdplus.vpd &
debug.v: dirs.v
$(VPD2VCD) +splitpacked $(SIM_DIR)/vcdplus.vpd $(SIM_DIR)/debug.vcd
$(MAKE) regen -C $(UNHARDWARE_DIR) MODEL=$(UNHARDWARE_MODEL) DATA=$(SIM_DIR)/debug.vcd BINARY=$(SIM_DIR)/prog.elf
clean.v:
@rm -rf results/vcs
@rm -rf reports/vcs
@rm -rf logs/vcs