blob: d3cd0030306e5a00d75b48849da4742fb0d731b6 [file] [log] [blame]
/*
:name: cont_assignment_delay
:description: continuous assignment with delay test
:should_fail: 0
:tags: 10.3.3
*/
module top(input a, input b);
wire w;
initial
w = #10 a & b;
endmodule