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chapter-6
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6.5--variable_mixed_assignments.sv
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/*
:name: variable_mixed_assignments
:description: Variable mixed assignments tests
:should_fail: 1
:tags: 6.5
:type: simulation
*/
module
top
();
wire clk
=
0
;
int
v
;
assign v
=
12
;
always
@(
posedge clk
)
v
<=
~
v
;
endmodule
