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foss-fpga-tools
/
third_party
/
Surelog
/
4a79a47b7dd03dd4b2776ee40322b0149935d234
/
.
/
src
/
Testcases
/
Yosys
/
lut
/
map_not.v
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module
top
();
input a
;
output y
;
assign y
=
~
a
;
endmodule
