src/Testcases/YosysBigSim/reed_solomon_decoder/YosysBigSimReed_diff.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0125] Cannot read the file's content "rtl/BM_lamda.v". Only UTF-8 is supported.

[WARNI:PA0205] rtl/GF_matrix_ascending_binary.v:20 No timescale set for "GF_matrix_ascending_binary".

[WARNI:PA0205] rtl/GF_matrix_dec.v:21 No timescale set for "GF_matrix_dec".

[WARNI:PA0205] rtl/DP_RAM.v:18 No timescale set for "DP_RAM".

[WARNI:PA0205] rtl/GF_mult_add_syndromes.v:28 No timescale set for "GF_mult_add_syndromes".

[WARNI:PA0205] rtl/RS_dec.v:21 No timescale set for "RS_dec".

[WARNI:PA0205] rtl/input_syndromes.v:24 No timescale set for "input_syndromes".

[WARNI:PA0205] rtl/Omega_Phy.v:21 No timescale set for "Omega_Phy".

[WARNI:PA0205] rtl/out_stage.v:21 No timescale set for "out_stage".

[WARNI:PA0205] rtl/transport_in2out.v:22 No timescale set for "transport_in2out".

[WARNI:PA0205] rtl/error_correction.v:20 No timescale set for "error_correction".

[WARNI:PA0205] rtl/lamda_roots.v:21 No timescale set for "lamda_roots".

[WARNI:PA0205] sim/RS_dec_tb.v:3 No timescale set for "testbench".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/DP_RAM.v:18 Compile module "work@DP_RAM".

[INFO :CP0303] rtl/Omega_Phy.v:21 Compile module "work@Omega_Phy".

[INFO :CP0303] rtl/lamda_roots.v:21 Compile module "work@lamda_roots".

[INFO :CP0303] rtl/GF_matrix_ascending_binary.v:20 Compile module "work@GF_matrix_ascending_binary".

[INFO :CP0303] rtl/RS_dec.v:21 Compile module "work@RS_dec".

[INFO :CP0303] rtl/out_stage.v:21 Compile module "work@out_stage".

[INFO :CP0303] rtl/GF_matrix_dec.v:21 Compile module "work@GF_matrix_dec".

[INFO :CP0303] rtl/error_correction.v:20 Compile module "work@error_correction".

[INFO :CP0303] sim/RS_dec_tb.v:3 Compile module "work@testbench".

[INFO :CP0303] rtl/GF_mult_add_syndromes.v:28 Compile module "work@GF_mult_add_syndromes".

[INFO :CP0303] rtl/input_syndromes.v:24 Compile module "work@input_syndromes".

[INFO :CP0303] rtl/transport_in2out.v:22 Compile module "work@transport_in2out".

[NOTE :CP0309] rtl/Omega_Phy.v:44 Implicit port type (wire) for "add_pow2",
there are 20 more instances of this message.

[NOTE :CP0309] rtl/lamda_roots.v:30 Implicit port type (wire) for "add_GF_dec1",
there are 8 more instances of this message.

[NOTE :CP0309] rtl/RS_dec.v:29 Implicit port type (wire) for "Out_byte",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/error_correction.v:44 Implicit port type (wire) for "add_pow2",
there are 8 more instances of this message.

[NOTE :CP0309] rtl/input_syndromes.v:38 Implicit port type (wire) for "s1",
there are 15 more instances of this message.

[NOTE :CP0309] rtl/transport_in2out.v:32 Implicit port type (wire) for "WE",
there are 1 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] sim/RS_dec_tb.v:3 Top level module "work@testbench".

[WARNI:EL0500] rtl/RS_dec.v:106 Cannot find a module definition for "work@RS_dec::BM_lamda".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 5.

[NOTE :EL0510] Nb instances: 26.

[NOTE :EL0511] Nb leaf instances: 1.

[WARNI:EL0512] Nb undefined modules: 1.

[WARNI:EL0513] Nb undefined instances: 1.

[  FATAL] : 0
[  ERROR] : 1
[WARNING] : 15
[   NOTE] : 11

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*   End SURELOG SVerilog Compiler/Linter   *
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7.98user 0.19system 0:02.72elapsed 300%CPU (0avgtext+0avgdata 114556maxresident)k
568inputs+328outputs (2major+28104minor)pagefaults 0swaps
sh: 2: -mt: not found