src/Testcases/YosysOldTests/openmsp430/YosysOldOpen_diff.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_all/surelog.log.

[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu".

[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate".

[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate".

[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module".

[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux".

[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk".

[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart".

[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg".

[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit".

[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend".

[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone".

[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier".

[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file".

[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux".

[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr".

[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".

[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".

[WARNI:PA0205] rtl/omsp_wakeup_cell.v:44 No timescale set for "omsp_wakeup_cell".

[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog".

[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu".

[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate".

[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate".

[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module".

[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux".

[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg".

[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk".

[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart".

[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit".

[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend".

[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone".

[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier".

[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file".

[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux".

[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr".

[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".

[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".

[INFO :CP0303] rtl/omsp_wakeup_cell.v:44 Compile module "work@omsp_wakeup_cell".

[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog".

[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430".

[INFO :CP0302] /home/alain/Surelog/src/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/Surelog/src/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/src/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out",
there are 3 more instances of this message.

[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y".

[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk".

[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk",
there are 14 more instances of this message.

[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out".

[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_freeze",
there are 8 more instances of this message.

[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff",
there are 11 more instances of this message.

[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq",
there are 11 more instances of this message.

[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din",
there are 15 more instances of this message.

[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout".

[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff",
there are 9 more instances of this message.

[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out".

[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id",
there are 5 more instances of this message.

[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".

[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".

[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout",
there are 3 more instances of this message.

[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk",
there are 24 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate".

[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate".

[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux".

[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk".

[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux".

[NOTE :EL0503] rtl/omsp_wakeup_cell.v:44 Top level module "work@omsp_wakeup_cell".

[NOTE :EL0503] rtl/openMSP430.v:46 Top level module "work@openMSP430".

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 7.

[NOTE :EL0509] Max instance depth: 4.

[NOTE :EL0510] Nb instances: 23.

[NOTE :EL0511] Nb leaf instances: 15.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 20
[   NOTE] : 31

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*   End SURELOG SVerilog Compiler/Linter   *
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8.68user 0.09system 0:08.78elapsed 99%CPU (0avgtext+0avgdata 163616maxresident)k
728inputs+6144outputs (0major+44700minor)pagefaults 0swaps
sh: 2: -mt: not found