src/Testcases/YosysOldTests/spi/YosysOldSpi_diff.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] rtl/spi_clgen.v:41 Cannot open include file "spi_defines.v".

[ERROR:PP0101] rtl/spi_clgen.v:42 Cannot open include file "timescale.v".

[ERROR:PP0102] rtl/spi_clgen.v:53 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_clgen.v:62 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_clgen.v:67 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_clgen.v:68 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_clgen.v:74 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_clgen.v:80 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0101] rtl/spi_shift.v:41 Cannot open include file "spi_defines.v".

[ERROR:PP0101] rtl/spi_shift.v:42 Cannot open include file "timescale.v".

[ERROR:PP0102] rtl/spi_shift.v:55 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:65 Unknown macro "SPI_MAX_CHAR".

[ERROR:PP0102] rtl/spi_shift.v:73 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:74 Unknown macro "SPI_MAX_CHAR".

[ERROR:PP0102] rtl/spi_shift.v:75 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:76 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:82 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:83 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:84 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:95 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:99 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:101 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:122 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_shift.v:129 Unknown macro "SPI_MAX_CHAR".

[ERROR:PP0102] rtl/spi_shift.v:234 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0101] rtl/spi_top.v:42 Cannot open include file "spi_defines.v".

[ERROR:PP0101] rtl/spi_top.v:43 Cannot open include file "timescale.v".

[ERROR:PP0102] rtl/spi_top.v:72 Unknown macro "SPI_SS_NB".

[ERROR:PP0102] rtl/spi_top.v:82 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_top.v:83 Unknown macro "SPI_CTRL_BIT_NB".

[ERROR:PP0102] rtl/spi_top.v:84 Unknown macro "SPI_SS_NB".

[ERROR:PP0102] rtl/spi_top.v:86 Unknown macro "SPI_MAX_CHAR".

[ERROR:PP0102] rtl/spi_top.v:89 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_DEVIDE".

[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_CTRL".

[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_TX_0".

[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_TX_1".

[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_TX_2".

[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_TX_3".

[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_SS".

[ERROR:PP0102] rtl/spi_top.v:115 Unknown macro "SPI_OFS_BITS".

[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_RX_0".

[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_MAX_CHAR".

[ERROR:PP0102] rtl/spi_top.v:129 Unknown macro "SPI_RX_1".

[ERROR:PP0102] rtl/spi_top.v:130 Unknown macro "SPI_RX_2".

[ERROR:PP0102] rtl/spi_top.v:131 Unknown macro "SPI_RX_3".

[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL".

[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL_BIT_NB".

[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DEVIDE".

[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS".

[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS_NB".

[ERROR:PP0102] rtl/spi_top.v:177 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PP0102] rtl/spi_top.v:215 Unknown macro "SPI_CTRL_BIT_NB".

[ERROR:PP0102] rtl/spi_top.v:221 Unknown macro "SPI_CTRL_BIT_NB".

[ERROR:PP0102] rtl/spi_top.v:224 Unknown macro "SPI_CTRL_GO".

[ERROR:PP0102] rtl/spi_top.v:227 Unknown macro "SPI_CTRL_RX_NEGEDGE".

[ERROR:PP0102] rtl/spi_top.v:228 Unknown macro "SPI_CTRL_TX_NEGEDGE".

[ERROR:PP0102] rtl/spi_top.v:229 Unknown macro "SPI_CTRL_GO".

[ERROR:PP0102] rtl/spi_top.v:230 Unknown macro "SPI_CTRL_CHAR_LEN".

[ERROR:PP0102] rtl/spi_top.v:231 Unknown macro "SPI_CTRL_LSB".

[ERROR:PP0102] rtl/spi_top.v:232 Unknown macro "SPI_CTRL_IE".

[ERROR:PP0102] rtl/spi_top.v:233 Unknown macro "SPI_CTRL_ASS".

[ERROR:PP0102] rtl/spi_top.v:239 Unknown macro "SPI_SS_NB".

[ERROR:PP0102] rtl/spi_top.v:273 Unknown macro "SPI_SS_NB".

[ERROR:PP0102] rtl/spi_top.v:279 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0207] timescale.v:11 Syntax error: no viable alternative at input 'input     [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!!',
  input     [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!! -1:0] divider;  // clock divider (output clock is divided by this value)
             ^-- ./slpp_unit/work/rtl/spi_clgen.v:51 col:13.

[ERROR:PA0203] timescale.v:11 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0203] timescale.v:25 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0203] timescale.v:26 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0203] timescale.v:32 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0203] timescale.v:38 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0207] rtl/spi_shift.v:53 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!!',
  input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!! -1:0] len;          // data len in bits (minus one)
         ^-- ./slpp_unit/work/rtl/spi_shift.v:53 col:9.

[ERROR:PA0203] rtl/spi_shift.v:53 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:80 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:81 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:82 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:93 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:97 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:99 Unknown macro "SPI_CHAR_LEN_BITS".

[ERROR:PA0203] rtl/spi_shift.v:127 Unknown macro "SPI_MAX_CHAR".

[ERROR:PA0207] rtl/spi_top.v:70 Syntax error: no viable alternative at input 'output          [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!!',
  output          [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!! -1:0] ss_pad_o;         // slave select
                   ^-- ./slpp_unit/work/rtl/spi_top.v:70 col:19.

[ERROR:PA0203] rtl/spi_top.v:70 Unknown macro "SPI_SS_NB".

[ERROR:PA0203] rtl/spi_top.v:102 Unknown macro "SPI_DEVIDE".

[ERROR:PA0203] rtl/spi_top.v:103 Unknown macro "SPI_CTRL".

[ERROR:PA0203] rtl/spi_top.v:104 Unknown macro "SPI_TX_0".

[ERROR:PA0203] rtl/spi_top.v:105 Unknown macro "SPI_TX_1".

[ERROR:PA0203] rtl/spi_top.v:106 Unknown macro "SPI_TX_2".

[ERROR:PA0203] rtl/spi_top.v:107 Unknown macro "SPI_TX_3".

[ERROR:PA0203] rtl/spi_top.v:108 Unknown macro "SPI_SS".

[ERROR:PA0203] rtl/spi_top.v:114 Unknown macro "SPI_RX_0".

[ERROR:PA0203] rtl/spi_top.v:114 Unknown macro "SPI_MAX_CHAR".

[ERROR:PA0203] rtl/spi_top.v:115 Unknown macro "SPI_RX_1".

[ERROR:PA0203] rtl/spi_top.v:116 Unknown macro "SPI_RX_2".

[ERROR:PA0203] rtl/spi_top.v:117 Unknown macro "SPI_RX_3".

[ERROR:PA0203] rtl/spi_top.v:118 Unknown macro "SPI_CTRL".

[ERROR:PA0203] rtl/spi_top.v:119 Unknown macro "SPI_DEVIDE".

[ERROR:PA0203] rtl/spi_top.v:120 Unknown macro "SPI_SS".

[ERROR:PA0203] rtl/spi_top.v:161 Unknown macro "SPI_DIVIDER_LEN".

[ERROR:PA0203] rtl/spi_top.v:171 Unknown macro "SPI_CTRL_BIT_NB".

[ERROR:PA0203] rtl/spi_top.v:195 Unknown macro "SPI_SS_NB".

[ERROR:PA0203] rtl/spi_top.v:201 Unknown macro "SPI_SS_NB".

[WARNI:PA0205] cache/synth.v:1 No timescale set for "spi_clgen".

[WARNI:PA0205] cache/synth.v:359 No timescale set for "spi_shift".

[WARNI:PA0205] cache/synth.v:4166 No timescale set for "spi_top".

[INFO :CP0300] Compilation...

[INFO :CP0303] cache/synth.v:1 Compile module "work@spi_clgen".

[INFO :CP0303] cache/synth.v:359 Compile module "work@spi_shift".

[INFO :CP0303] cache/synth.v:4166 Compile module "work@spi_top".

[NOTE :CP0309] cache/synth.v:359 Implicit port type (wire) for "last",
there are 1 more instances of this message.

[NOTE :CP0309] cache/synth.v:4166 Implicit port type (wire) for "wb_err_o",
there are 3 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] cache/synth.v:4166 Top level module "work@spi_top".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 3.

[NOTE :EL0511] Nb leaf instances: 2.

[  FATAL] : 0
[  ERROR] : 109
[WARNING] : 3
[   NOTE] : 7

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*   End SURELOG SVerilog Compiler/Linter   *
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7.22user 0.14system 0:03.43elapsed 214%CPU (0avgtext+0avgdata 127036maxresident)k
392inputs+704outputs (0major+31778minor)pagefaults 0swaps
sh: 2: -mt: not found