| |
| /-----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \-----------------------------------------------------------------------------/ |
| |
| |
| -- Executing script file `scripts/synth.ys' -- |
| |
| 1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/pcm_slv_top.v |
| Parsing Verilog input from `rtl/pcm_slv_top.v' to AST representation. |
| Generating RTLIL representation for module `\pcm_slv_top'. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing HIERARCHY pass (managing design hierarchy). |
| Full command line: hierarchy -top pcm_slv_top |
| Top module: \pcm_slv_top |
| Removed 0 unused modules. |
| Top module: \pcm_slv_top |
| Removed 0 unused modules. |
| |
| -- Executing script file `../scripts/generic.ys' -- |
| |
| 3. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 4. Executing PROC pass (convert processes to netlists). |
| |
| 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed a total of 0 dead cases. |
| |
| 4.3. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 4.4. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:121$1'. |
| creating decoder for signal `$0\pclk_t[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:124$2'. |
| creating decoder for signal `$0\pclk_s[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:127$3'. |
| creating decoder for signal `$0\pclk_r[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:138$8'. |
| creating decoder for signal `$0\pcm_sync_r1[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:141$9'. |
| creating decoder for signal `$0\psa[7:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:144$10'. |
| creating decoder for signal `$0\pcm_sync_r2[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:147$12'. |
| creating decoder for signal `$0\pcm_sync_r3[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:150$13'. |
| creating decoder for signal `$0\psync[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:160$17'. |
| creating decoder for signal `$0\tx_hold_byte_h[7:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:163$18'. |
| creating decoder for signal `$0\tx_hold_byte_l[7:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:166$19'. |
| creating decoder for signal `$0\tx_go[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:173$21'. |
| creating decoder for signal `$0\tx_hold_reg[15:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:182$23'. |
| creating decoder for signal `$0\tx_cnt[3:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:194$28'. |
| creating decoder for signal `$0\tx_go_r1[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:197$29'. |
| creating decoder for signal `$0\tx_go_r2[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:201$30'. |
| creating decoder for signal `$0\rxd_t[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:204$31'. |
| creating decoder for signal `$0\rxd[0:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:209$34'. |
| creating decoder for signal `$0\rx_hold_reg[15:0]'. |
| Creating decoders for process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:214$36'. |
| creating decoder for signal `$0\rx_reg[15:0]'. |
| |
| 4.5. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\pcm_slv_top.\pclk_t' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:121$1'. |
| created $dff cell `$procdff$99' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\pclk_s' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:124$2'. |
| created $dff cell `$procdff$100' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\pclk_r' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:127$3'. |
| created $dff cell `$procdff$101' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\pcm_sync_r1' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:138$8'. |
| created $dff cell `$procdff$102' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\psa' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:141$9'. |
| created $dff cell `$procdff$103' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\pcm_sync_r2' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:144$10'. |
| created $dff cell `$procdff$104' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\pcm_sync_r3' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:147$12'. |
| created $dff cell `$procdff$105' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\psync' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:150$13'. |
| created $dff cell `$procdff$106' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_hold_byte_h' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:160$17'. |
| created $dff cell `$procdff$107' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_hold_byte_l' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:163$18'. |
| created $dff cell `$procdff$108' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_go' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:166$19'. |
| created $dff cell `$procdff$109' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_hold_reg' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:173$21'. |
| created $dff cell `$procdff$110' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_cnt' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:182$23'. |
| created $dff cell `$procdff$111' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_go_r1' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:194$28'. |
| created $dff cell `$procdff$112' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\tx_go_r2' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:197$29'. |
| created $dff cell `$procdff$113' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\rxd_t' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:201$30'. |
| created $dff cell `$procdff$114' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\rxd' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:204$31'. |
| created $dff cell `$procdff$115' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\rx_hold_reg' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:209$34'. |
| created $dff cell `$procdff$116' with positive edge clock. |
| Creating register for signal `\pcm_slv_top.\rx_reg' using process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:214$36'. |
| created $dff cell `$procdff$117' with positive edge clock. |
| |
| 4.6. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:121$1'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:124$2'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:127$3'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:138$8'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:138$8'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:141$9'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:141$9'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:144$10'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:147$12'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:150$13'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:160$17'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:160$17'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:163$18'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:163$18'. |
| Found and cleaned up 3 empty switches in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:166$19'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:166$19'. |
| Found and cleaned up 3 empty switches in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:173$21'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:173$21'. |
| Found and cleaned up 2 empty switches in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:182$23'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:182$23'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:194$28'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:194$28'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:197$29'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:197$29'. |
| Found and cleaned up 1 empty switch in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:201$30'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:201$30'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:204$31'. |
| Found and cleaned up 2 empty switches in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:209$34'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:209$34'. |
| Found and cleaned up 2 empty switches in `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:214$36'. |
| Removing empty process `\pcm_slv_top.$proc$rtl/pcm_slv_top.v:214$36'. |
| Cleaned up 19 empty switches. |
| |
| 5. Executing OPT pass (performing simple optimizations). |
| |
| 5.1. Optimizing in-memory representation of design. |
| |
| 5.2. Executing OPT_CONST pass (perform const folding). |
| |
| 5.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\pcm_slv_top'. |
| Cell `$logic_not$rtl/pcm_slv_top.v:174$22' is identical to cell `$logic_not$rtl/pcm_slv_top.v:167$20'. |
| Redirecting output \Y: $logic_not$rtl/pcm_slv_top.v:174$22_Y = $logic_not$rtl/pcm_slv_top.v:167$20_Y |
| Removing $logic_not cell `$logic_not$rtl/pcm_slv_top.v:174$22' from module `\pcm_slv_top'. |
| Cell `$logic_not$rtl/pcm_slv_top.v:183$24' is identical to cell `$logic_not$rtl/pcm_slv_top.v:167$20'. |
| Redirecting output \Y: $logic_not$rtl/pcm_slv_top.v:183$24_Y = $logic_not$rtl/pcm_slv_top.v:167$20_Y |
| Removing $logic_not cell `$logic_not$rtl/pcm_slv_top.v:183$24' from module `\pcm_slv_top'. |
| Cell `$logic_not$rtl/pcm_slv_top.v:210$35' is identical to cell `$logic_not$rtl/pcm_slv_top.v:167$20'. |
| Redirecting output \Y: $logic_not$rtl/pcm_slv_top.v:210$35_Y = $logic_not$rtl/pcm_slv_top.v:167$20_Y |
| Removing $logic_not cell `$logic_not$rtl/pcm_slv_top.v:210$35' from module `\pcm_slv_top'. |
| Cell `$logic_not$rtl/pcm_slv_top.v:215$37' is identical to cell `$logic_not$rtl/pcm_slv_top.v:167$20'. |
| Redirecting output \Y: $logic_not$rtl/pcm_slv_top.v:215$37_Y = $logic_not$rtl/pcm_slv_top.v:167$20_Y |
| Removing $logic_not cell `$logic_not$rtl/pcm_slv_top.v:215$37' from module `\pcm_slv_top'. |
| Removed a total of 4 cells. |
| |
| 5.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 5.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 5.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 5.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 5.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| removing unused `$mux' cell `$procmux$82'. |
| removing unused `$dff' cell `$procdff$113'. |
| removing unused non-port wire \tx_go_r2. |
| removed 50 unused temporary wires. |
| |
| 5.9. Executing OPT_CONST pass (perform const folding). |
| |
| 5.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 5.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 5.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 5.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| |
| 5.16. Executing OPT_CONST pass (perform const folding). |
| |
| 5.17. Optimizing in-memory representation of design. |
| |
| 5.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 6. Executing MEMORY pass. |
| |
| 6.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| |
| 6.2. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 6.3. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| |
| 7. Executing OPT pass (performing simple optimizations). |
| |
| 7.1. Optimizing in-memory representation of design. |
| |
| 7.2. Executing OPT_CONST pass (perform const folding). |
| |
| 7.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 7.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 7.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 7.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 7.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 7.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| |
| 7.9. Executing OPT_CONST pass (perform const folding). |
| |
| 7.10. Optimizing in-memory representation of design. |
| |
| 7.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 8. Executing TECHMAP pass (map to technology primitives). |
| |
| 8.1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog <stdcells.v> |
| Parsing Verilog input from `<stdcells.v>' to AST representation. |
| Generating RTLIL representation for module `\$not'. |
| Generating RTLIL representation for module `\$pos'. |
| Generating RTLIL representation for module `\$neg'. |
| Generating RTLIL representation for module `\$and'. |
| Generating RTLIL representation for module `\$or'. |
| Generating RTLIL representation for module `\$xor'. |
| Generating RTLIL representation for module `\$xnor'. |
| Generating RTLIL representation for module `\$reduce_and'. |
| Generating RTLIL representation for module `\$reduce_or'. |
| Generating RTLIL representation for module `\$reduce_xor'. |
| Generating RTLIL representation for module `\$reduce_xnor'. |
| Generating RTLIL representation for module `\$reduce_bool'. |
| Generating RTLIL representation for module `\$shift'. |
| Generating RTLIL representation for module `\$shl'. |
| Generating RTLIL representation for module `\$shr'. |
| Generating RTLIL representation for module `\$sshl'. |
| Generating RTLIL representation for module `\$sshr'. |
| Generating RTLIL representation for module `\$fulladd'. |
| Generating RTLIL representation for module `\$alu'. |
| Generating RTLIL representation for module `\$lt'. |
| Generating RTLIL representation for module `\$le'. |
| Generating RTLIL representation for module `\$eq'. |
| Generating RTLIL representation for module `\$ne'. |
| Generating RTLIL representation for module `\$ge'. |
| Generating RTLIL representation for module `\$gt'. |
| Generating RTLIL representation for module `\$add'. |
| Generating RTLIL representation for module `\$sub'. |
| Generating RTLIL representation for module `\$logic_not'. |
| Generating RTLIL representation for module `\$logic_and'. |
| Generating RTLIL representation for module `\$logic_or'. |
| Generating RTLIL representation for module `\$mux'. |
| Generating RTLIL representation for module `\$pmux'. |
| Generating RTLIL representation for module `\$safe_pmux'. |
| Generating RTLIL representation for module `\$dff'. |
| Generating RTLIL representation for module `\$adff'. |
| Successfully finished Verilog frontend. |
| |
| 8.2. Executing AST frontend in derive mode using pre-parsed AST for module `$add'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.3. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.4. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.5. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:130$5' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:131$7' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:151$15' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:158$16' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:187$27' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:207$33' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$39' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$40' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.6. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 8.7. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$eq$rtl/pcm_slv_top.v:187$26' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 8.8. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.9. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:130$4' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:131$6' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:151$14' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:167$20' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:217$38' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.10. Executing AST frontend in derive mode using pre-parsed AST for module `$or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.11. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$or$rtl/pcm_slv_top.v:207$32' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.12. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 8.13. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procdff$100' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$101' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$102' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 8.14. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 8.15. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procdff$103' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$104' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$105' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$106' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$107' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$108' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$109' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 8.16. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 16 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=16\CLK_POLARITY=1'1'. |
| |
| 8.17. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procdff$110' using `$paramod$dff\WIDTH=16\CLK_POLARITY=1'1'. |
| |
| 8.18. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 4 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=4\CLK_POLARITY=1'1'. |
| |
| 8.19. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procdff$111' using `$paramod$dff\WIDTH=4\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$112' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$114' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$115' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$116' using `$paramod$dff\WIDTH=16\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$117' using `$paramod$dff\WIDTH=16\CLK_POLARITY=1'1'. |
| Mapping `pcm_slv_top.$procdff$99' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 8.20. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=1'. |
| |
| 8.21. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procmux$43' using `$paramod$mux\WIDTH=1'. |
| |
| 8.22. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=8'. |
| |
| 8.23. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procmux$46' using `$paramod$mux\WIDTH=8'. |
| Mapping `pcm_slv_top.$procmux$49' using `$paramod$mux\WIDTH=8'. |
| Mapping `pcm_slv_top.$procmux$52' using `$paramod$mux\WIDTH=8'. |
| Mapping `pcm_slv_top.$procmux$55' using `$paramod$mux\WIDTH=1'. |
| Mapping `pcm_slv_top.$procmux$58' using `$paramod$mux\WIDTH=1'. |
| Mapping `pcm_slv_top.$procmux$61' using `$paramod$mux\WIDTH=1'. |
| |
| 8.24. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=16'. |
| |
| 8.25. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procmux$64' using `$paramod$mux\WIDTH=16'. |
| Mapping `pcm_slv_top.$procmux$67' using `$paramod$mux\WIDTH=16'. |
| Mapping `pcm_slv_top.$procmux$70' using `$paramod$mux\WIDTH=16'. |
| |
| 8.26. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=4'. |
| |
| 8.27. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$procmux$73' using `$paramod$mux\WIDTH=4'. |
| Mapping `pcm_slv_top.$procmux$76' using `$paramod$mux\WIDTH=4'. |
| Mapping `pcm_slv_top.$procmux$79' using `$paramod$mux\WIDTH=1'. |
| Mapping `pcm_slv_top.$procmux$85' using `$paramod$mux\WIDTH=1'. |
| Mapping `pcm_slv_top.$procmux$88' using `$paramod$mux\WIDTH=16'. |
| Mapping `pcm_slv_top.$procmux$91' using `$paramod$mux\WIDTH=16'. |
| Mapping `pcm_slv_top.$procmux$94' using `$paramod$mux\WIDTH=16'. |
| Mapping `pcm_slv_top.$procmux$97' using `$paramod$mux\WIDTH=16'. |
| |
| 8.28. Executing AST frontend in derive mode using pre-parsed AST for module `$shr'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$shr\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=3\Y_WIDTH=1'. |
| |
| 8.29. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11' using `$paramod$shr\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$ternary$rtl/pcm_slv_top.v:219$41' using `$paramod$mux\WIDTH=8'. |
| |
| 8.30. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.31. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.32. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=4'. |
| |
| 8.33. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.alu' using `$paramod$alu\WIDTH=4'. |
| |
| 8.34. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.35. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:130$5.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:130$5.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:131$7.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:131$7.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:151$15.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:151$15.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:158$16.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:158$16.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:187$27.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:187$27.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:207$33.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:207$33.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$39.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$39.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$40.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$and$rtl/pcm_slv_top.v:217$40.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$eq$rtl/pcm_slv_top.v:187$26.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `pcm_slv_top.$eq$rtl/pcm_slv_top.v:187$26.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.36. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_bool'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| |
| 8.37. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:130$4.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:131$6.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:151$14.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:167$20.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `pcm_slv_top.$logic_not$rtl/pcm_slv_top.v:217$38.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `pcm_slv_top.$or$rtl/pcm_slv_top.v:207$32.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$or$rtl/pcm_slv_top.v:207$32.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[0].mux' using `$paramod$mux\WIDTH=8'. |
| |
| 8.38. Executing AST frontend in derive mode using pre-parsed AST for module `$shift'. |
| Parameter \WIDTH = 8 |
| Parameter \SHIFT = 1 |
| Generating RTLIL representation for module `$paramod$shift\WIDTH=8\SHIFT=1'. |
| |
| 8.39. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[0].sh' using `$paramod$shift\WIDTH=8\SHIFT=1'. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[1].mux' using `$paramod$mux\WIDTH=8'. |
| |
| 8.40. Executing AST frontend in derive mode using pre-parsed AST for module `$shift'. |
| Parameter \WIDTH = 8 |
| Parameter \SHIFT = 2 |
| Generating RTLIL representation for module `$paramod$shift\WIDTH=8\SHIFT=2'. |
| |
| 8.41. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[1].sh' using `$paramod$shift\WIDTH=8\SHIFT=2'. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[2].mux' using `$paramod$mux\WIDTH=8'. |
| |
| 8.42. Executing AST frontend in derive mode using pre-parsed AST for module `$shift'. |
| Parameter \WIDTH = 8 |
| Parameter \SHIFT = 4 |
| Generating RTLIL representation for module `$paramod$shift\WIDTH=8\SHIFT=4'. |
| |
| 8.43. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.V[2].sh' using `$paramod$shift\WIDTH=8\SHIFT=4'. |
| |
| 8.44. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| |
| 8.45. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$shr$rtl/pcm_slv_top.v:145$11.expand' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| |
| 8.46. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.47. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$techmap$eq$rtl/pcm_slv_top.v:187$26.$not$<stdcells.v>:808$147' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 8.48. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 8.49. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$techmap$eq$rtl/pcm_slv_top.v:187$26.$reduce_or$<stdcells.v>:808$146' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 8.50. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.51. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder' using `$fulladd'. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder' using `$fulladd'. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder' using `$fulladd'. |
| Mapping `pcm_slv_top.$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder' using `$fulladd'. |
| |
| 8.52. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 8.53. Continuing TECHMAP pass. |
| Mapping `pcm_slv_top.$techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `pcm_slv_top.$techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| No more expansions possible. |
| |
| 9. Executing OPT pass (performing simple optimizations). |
| |
| 9.1. Optimizing in-memory representation of design. |
| |
| 9.2. Executing OPT_CONST pass (perform const folding). |
| Replacing $_AND_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.gate1' (?1) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.t1 = $procdff$111.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.gate3' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.gate4' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.Y = $add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.gate1' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.gate2' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.t2 = $procdff$111.Q [1]'. |
| Replacing $_AND_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.gate1' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.gate2' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.t2 = $procdff$111.Q [2]'. |
| Replacing $_AND_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.gate1' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.gate2' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.t2 = $procdff$111.Q [3]'. |
| Replacing $_OR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.gate5' (?0) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.X = $procdff$111.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.gate5' (0?) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.X = $add$rtl/pcm_slv_top.v:185$25.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.gate5' (0?) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.X = $add$rtl/pcm_slv_top.v:185$25.alu.V[2].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.gate5' (0?) in module `\pcm_slv_top' with constant driver `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.X = $add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.t3'. |
| |
| 9.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\pcm_slv_top'. |
| Cell `$techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145.V[0].gate' is identical to cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.gate2'. |
| Redirecting output \Y: $techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145.Y [0] = $add$rtl/pcm_slv_top.v:185$25.alu.V[0].adder.t2 |
| Removing $_XOR_ cell `$techmap$eq$rtl/pcm_slv_top.v:187$26.$xor$<stdcells.v>:808$145.V[0].gate' from module `\pcm_slv_top'. |
| Removed a total of 1 cells. |
| |
| 9.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 9.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 9.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 9.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 9.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[0].mux.V[1].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[0].mux.V[3].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[5].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[5].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[0].mux.V[5].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[0].mux.V[7].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[6].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[4].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[1].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[3].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[7].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[6].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[3].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[1].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[2].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[1].mux.V[7].gate'. |
| removing unused `$_MUX_' cell `$shr$rtl/pcm_slv_top.v:145$11.V[2].mux.V[2].gate'. |
| removing unused `$_AND_' cell `$add$rtl/pcm_slv_top.v:185$25.alu.V[3].adder.gate3'. |
| removed 347 unused temporary wires. |
| |
| 9.9. Executing OPT_CONST pass (perform const folding). |
| |
| 9.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 9.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 9.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 9.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 9.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 9.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| |
| 9.16. Executing OPT_CONST pass (perform const folding). |
| |
| 9.17. Optimizing in-memory representation of design. |
| |
| 9.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 10. Executing ABC pass (technology mapping using ABC). |
| |
| 10.1. Extracting gate logic of module `\pcm_slv_top' to `/tmp/yosys-abc-nOH2OK/input.v'.. |
| Extracted 192 gates and 297 wires to a logic network with 103 inputs and 90 outputs. |
| |
| 10.1.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-nOH2OK/input.v; read_library /tmp/yosys-abc-nOH2OK/stdcells.genlib; map; write_verilog /tmp/yosys-abc-nOH2OK/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-nOH2OK/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-nOH2OK/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-nOH2OK/stdcells.super". Time = 0.00 sec |
| |
| 10.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 63 |
| ABC RESULTS: INV cells: 9 |
| ABC RESULTS: MUX cells: 107 |
| ABC RESULTS: OR cells: 9 |
| ABC RESULTS: XOR cells: 4 |
| ABC RESULTS: internal signals: 104 |
| ABC RESULTS: input signals: 103 |
| ABC RESULTS: output signals: 90 |
| |
| 10.1.3. Removing temp directory `/tmp/yosys-abc-nOH2OK': |
| Removing `/tmp/yosys-abc-nOH2OK/input.v'. |
| Removing `/tmp/yosys-abc-nOH2OK/output.v'. |
| Removing `/tmp/yosys-abc-nOH2OK/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-nOH2OK/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-nOH2OK/stdcells.super'. |
| Removing `/tmp/yosys-abc-nOH2OK'. |
| |
| 11. Executing OPT pass (performing simple optimizations). |
| |
| 11.1. Optimizing in-memory representation of design. |
| |
| 11.2. Executing OPT_CONST pass (perform const folding). |
| |
| 11.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 11.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \pcm_slv_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \pcm_slv_top. |
| Performed a total of 0 changes. |
| |
| 11.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\pcm_slv_top'. |
| Removed a total of 0 cells. |
| |
| 11.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 11.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \pcm_slv_top.. |
| removing unused non-port wire \pclk_fal. |
| removing unused non-port wire \pclk_ris. |
| removing unused non-port wire \rx_data_le. |
| removing unused non-port wire \tx_data_le. |
| removing unused non-port wire \tx_done. |
| removed 222 unused temporary wires. |
| |
| 11.9. Executing OPT_CONST pass (perform const folding). |
| |
| 11.10. Optimizing in-memory representation of design. |
| |
| 11.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 12. Executing Verilog backend. |
| Full command line: write_verilog -noattr output/synth.v |
| Dumping module `\pcm_slv_top'. |
| renaming `$0\pcm_sync_r1[0:0]' to `_000_'. |
| renaming `$0\pcm_sync_r2[0:0]' to `_001_'. |
| renaming `$0\psa[7:0]' to `_002_'. |
| renaming `$0\psync[0:0]' to `_003_'. |
| renaming `$0\rx_hold_reg[15:0]' to `_004_'. |
| renaming `$0\rx_reg[15:0]' to `_005_'. |
| renaming `$0\rxd_t[0:0]' to `_006_'. |
| renaming `$0\tx_cnt[3:0]' to `_007_'. |
| renaming `$0\tx_go[0:0]' to `_008_'. |
| renaming `$0\tx_go_r1[0:0]' to `_009_'. |
| renaming `$0\tx_hold_byte_h[7:0]' to `_010_'. |
| renaming `$0\tx_hold_byte_l[7:0]' to `_011_'. |
| renaming `$0\tx_hold_reg[15:0]' to `_012_'. |
| renaming `$abc$148$g000' to `_115_'. |
| renaming `$abc$148$g001' to `_116_'. |
| renaming `$abc$148$g002' to `_117_'. |
| renaming `$abc$148$g003' to `_118_'. |
| renaming `$abc$148$g004' to `_119_'. |
| renaming `$abc$148$g005' to `_120_'. |
| renaming `$abc$148$g006' to `_121_'. |
| renaming `$abc$148$g007' to `_122_'. |
| renaming `$abc$148$g008' to `_123_'. |
| renaming `$abc$148$g009' to `_124_'. |
| renaming `$abc$148$g010' to `_125_'. |
| renaming `$abc$148$g011' to `_126_'. |
| renaming `$abc$148$g012' to `_127_'. |
| renaming `$abc$148$g013' to `_128_'. |
| renaming `$abc$148$g014' to `_129_'. |
| renaming `$abc$148$g015' to `_130_'. |
| renaming `$abc$148$g016' to `_131_'. |
| renaming `$abc$148$g017' to `_132_'. |
| renaming `$abc$148$g018' to `_133_'. |
| renaming `$abc$148$g019' to `_134_'. |
| renaming `$abc$148$g020' to `_135_'. |
| renaming `$abc$148$g021' to `_136_'. |
| renaming `$abc$148$g022' to `_137_'. |
| renaming `$abc$148$g023' to `_138_'. |
| renaming `$abc$148$g024' to `_139_'. |
| renaming `$abc$148$g025' to `_140_'. |
| renaming `$abc$148$g026' to `_141_'. |
| renaming `$abc$148$g027' to `_142_'. |
| renaming `$abc$148$g028' to `_143_'. |
| renaming `$abc$148$g029' to `_144_'. |
| renaming `$abc$148$g030' to `_145_'. |
| renaming `$abc$148$g031' to `_146_'. |
| renaming `$abc$148$g032' to `_147_'. |
| renaming `$abc$148$g033' to `_148_'. |
| renaming `$abc$148$g034' to `_149_'. |
| renaming `$abc$148$g035' to `_150_'. |
| renaming `$abc$148$g036' to `_151_'. |
| renaming `$abc$148$g037' to `_152_'. |
| renaming `$abc$148$g038' to `_153_'. |
| renaming `$abc$148$g039' to `_154_'. |
| renaming `$abc$148$g040' to `_155_'. |
| renaming `$abc$148$g041' to `_156_'. |
| renaming `$abc$148$g042' to `_157_'. |
| renaming `$abc$148$g043' to `_158_'. |
| renaming `$abc$148$g044' to `_159_'. |
| renaming `$abc$148$g045' to `_160_'. |
| renaming `$abc$148$g046' to `_161_'. |
| renaming `$abc$148$g047' to `_162_'. |
| renaming `$abc$148$g048' to `_163_'. |
| renaming `$abc$148$g049' to `_164_'. |
| renaming `$abc$148$g050' to `_165_'. |
| renaming `$abc$148$g051' to `_166_'. |
| renaming `$abc$148$g052' to `_167_'. |
| renaming `$abc$148$g053' to `_168_'. |
| renaming `$abc$148$g054' to `_169_'. |
| renaming `$abc$148$g055' to `_170_'. |
| renaming `$abc$148$g056' to `_171_'. |
| renaming `$abc$148$g057' to `_172_'. |
| renaming `$abc$148$g058' to `_173_'. |
| renaming `$abc$148$g059' to `_174_'. |
| renaming `$abc$148$g060' to `_175_'. |
| renaming `$abc$148$g061' to `_176_'. |
| renaming `$abc$148$g062' to `_177_'. |
| renaming `$abc$148$g063' to `_178_'. |
| renaming `$abc$148$g064' to `_179_'. |
| renaming `$abc$148$g065' to `_180_'. |
| renaming `$abc$148$g066' to `_181_'. |
| renaming `$abc$148$g067' to `_182_'. |
| renaming `$abc$148$g068' to `_183_'. |
| renaming `$abc$148$g069' to `_184_'. |
| renaming `$abc$148$g070' to `_185_'. |
| renaming `$abc$148$g071' to `_186_'. |
| renaming `$abc$148$g072' to `_187_'. |
| renaming `$abc$148$g073' to `_188_'. |
| renaming `$abc$148$g074' to `_189_'. |
| renaming `$abc$148$g075' to `_190_'. |
| renaming `$abc$148$g076' to `_191_'. |
| renaming `$abc$148$g077' to `_192_'. |
| renaming `$abc$148$g078' to `_193_'. |
| renaming `$abc$148$g079' to `_194_'. |
| renaming `$abc$148$g080' to `_195_'. |
| renaming `$abc$148$g081' to `_196_'. |
| renaming `$abc$148$g082' to `_197_'. |
| renaming `$abc$148$g083' to `_198_'. |
| renaming `$abc$148$g084' to `_199_'. |
| renaming `$abc$148$g085' to `_200_'. |
| renaming `$abc$148$g086' to `_201_'. |
| renaming `$abc$148$g087' to `_202_'. |
| renaming `$abc$148$g088' to `_203_'. |
| renaming `$abc$148$g089' to `_204_'. |
| renaming `$abc$148$g090' to `_205_'. |
| renaming `$abc$148$g091' to `_206_'. |
| renaming `$abc$148$g092' to `_207_'. |
| renaming `$abc$148$g093' to `_208_'. |
| renaming `$abc$148$g094' to `_209_'. |
| renaming `$abc$148$g095' to `_210_'. |
| renaming `$abc$148$g096' to `_211_'. |
| renaming `$abc$148$g097' to `_212_'. |
| renaming `$abc$148$g098' to `_213_'. |
| renaming `$abc$148$g099' to `_214_'. |
| renaming `$abc$148$g100' to `_215_'. |
| renaming `$abc$148$g101' to `_216_'. |
| renaming `$abc$148$g102' to `_217_'. |
| renaming `$abc$148$g103' to `_218_'. |
| renaming `$abc$148$g104' to `_219_'. |
| renaming `$abc$148$g105' to `_220_'. |
| renaming `$abc$148$g106' to `_221_'. |
| renaming `$abc$148$g107' to `_222_'. |
| renaming `$abc$148$g108' to `_223_'. |
| renaming `$abc$148$g109' to `_224_'. |
| renaming `$abc$148$g110' to `_225_'. |
| renaming `$abc$148$g111' to `_226_'. |
| renaming `$abc$148$g112' to `_227_'. |
| renaming `$abc$148$g113' to `_228_'. |
| renaming `$abc$148$g114' to `_229_'. |
| renaming `$abc$148$g115' to `_230_'. |
| renaming `$abc$148$g116' to `_231_'. |
| renaming `$abc$148$g117' to `_232_'. |
| renaming `$abc$148$g118' to `_233_'. |
| renaming `$abc$148$g119' to `_234_'. |
| renaming `$abc$148$g120' to `_235_'. |
| renaming `$abc$148$g121' to `_236_'. |
| renaming `$abc$148$g122' to `_237_'. |
| renaming `$abc$148$g123' to `_238_'. |
| renaming `$abc$148$g124' to `_239_'. |
| renaming `$abc$148$g125' to `_240_'. |
| renaming `$abc$148$g126' to `_241_'. |
| renaming `$abc$148$g127' to `_242_'. |
| renaming `$abc$148$g128' to `_243_'. |
| renaming `$abc$148$g129' to `_244_'. |
| renaming `$abc$148$g130' to `_245_'. |
| renaming `$abc$148$g131' to `_246_'. |
| renaming `$abc$148$g132' to `_247_'. |
| renaming `$abc$148$g133' to `_248_'. |
| renaming `$abc$148$g134' to `_249_'. |
| renaming `$abc$148$g135' to `_250_'. |
| renaming `$abc$148$g136' to `_251_'. |
| renaming `$abc$148$g137' to `_252_'. |
| renaming `$abc$148$g138' to `_253_'. |
| renaming `$abc$148$g139' to `_254_'. |
| renaming `$abc$148$g140' to `_255_'. |
| renaming `$abc$148$g141' to `_256_'. |
| renaming `$abc$148$g142' to `_257_'. |
| renaming `$abc$148$g143' to `_258_'. |
| renaming `$abc$148$g144' to `_259_'. |
| renaming `$abc$148$g145' to `_260_'. |
| renaming `$abc$148$g146' to `_261_'. |
| renaming `$abc$148$g147' to `_262_'. |
| renaming `$abc$148$g148' to `_263_'. |
| renaming `$abc$148$g149' to `_264_'. |
| renaming `$abc$148$g150' to `_265_'. |
| renaming `$abc$148$g151' to `_266_'. |
| renaming `$abc$148$g152' to `_267_'. |
| renaming `$abc$148$g153' to `_268_'. |
| renaming `$abc$148$g154' to `_269_'. |
| renaming `$abc$148$g155' to `_270_'. |
| renaming `$abc$148$g156' to `_271_'. |
| renaming `$abc$148$g157' to `_272_'. |
| renaming `$abc$148$g158' to `_273_'. |
| renaming `$abc$148$g159' to `_274_'. |
| renaming `$abc$148$g160' to `_275_'. |
| renaming `$abc$148$g161' to `_276_'. |
| renaming `$abc$148$g162' to `_277_'. |
| renaming `$abc$148$g163' to `_278_'. |
| renaming `$abc$148$g164' to `_279_'. |
| renaming `$abc$148$g165' to `_280_'. |
| renaming `$abc$148$g166' to `_281_'. |
| renaming `$abc$148$g167' to `_282_'. |
| renaming `$abc$148$g168' to `_283_'. |
| renaming `$abc$148$g169' to `_284_'. |
| renaming `$abc$148$g170' to `_285_'. |
| renaming `$abc$148$g171' to `_286_'. |
| renaming `$abc$148$g172' to `_287_'. |
| renaming `$abc$148$g173' to `_288_'. |
| renaming `$abc$148$g174' to `_289_'. |
| renaming `$abc$148$g175' to `_290_'. |
| renaming `$abc$148$g176' to `_291_'. |
| renaming `$abc$148$g177' to `_292_'. |
| renaming `$abc$148$g178' to `_293_'. |
| renaming `$abc$148$g179' to `_294_'. |
| renaming `$abc$148$g180' to `_295_'. |
| renaming `$abc$148$g181' to `_296_'. |
| renaming `$abc$148$g182' to `_297_'. |
| renaming `$abc$148$g183' to `_298_'. |
| renaming `$abc$148$g184' to `_299_'. |
| renaming `$abc$148$g185' to `_300_'. |
| renaming `$abc$148$g186' to `_301_'. |
| renaming `$abc$148$g187' to `_302_'. |
| renaming `$abc$148$g188' to `_303_'. |
| renaming `$abc$148$g189' to `_304_'. |
| renaming `$abc$148$g190' to `_305_'. |
| renaming `$abc$148$g191' to `_306_'. |
| renaming `$abc$148$n193_1' to `_013_'. |
| renaming `$abc$148$n195_1' to `_014_'. |
| renaming `$abc$148$n196' to `_015_'. |
| renaming `$abc$148$n198' to `_016_'. |
| renaming `$abc$148$n223_1' to `_017_'. |
| renaming `$abc$148$n224_1' to `_018_'. |
| renaming `$abc$148$n225' to `_019_'. |
| renaming `$abc$148$n226_1' to `_020_'. |
| renaming `$abc$148$n227' to `_021_'. |
| renaming `$abc$148$n228_1' to `_022_'. |
| renaming `$abc$148$n229' to `_023_'. |
| renaming `$abc$148$n230_1' to `_024_'. |
| renaming `$abc$148$n231' to `_025_'. |
| renaming `$abc$148$n232_1' to `_026_'. |
| renaming `$abc$148$n233' to `_027_'. |
| renaming `$abc$148$n234_1' to `_028_'. |
| renaming `$abc$148$n235' to `_029_'. |
| renaming `$abc$148$n236_1' to `_030_'. |
| renaming `$abc$148$n238_1' to `_031_'. |
| renaming `$abc$148$n239' to `_032_'. |
| renaming `$abc$148$n240_1' to `_033_'. |
| renaming `$abc$148$n241' to `_034_'. |
| renaming `$abc$148$n243' to `_035_'. |
| renaming `$abc$148$n244_1' to `_036_'. |
| renaming `$abc$148$n246_1' to `_037_'. |
| renaming `$abc$148$n247' to `_038_'. |
| renaming `$abc$148$n249' to `_039_'. |
| renaming `$abc$148$n250_1' to `_040_'. |
| renaming `$abc$148$n252_1' to `_041_'. |
| renaming `$abc$148$n253' to `_042_'. |
| renaming `$abc$148$n255' to `_043_'. |
| renaming `$abc$148$n256_1' to `_044_'. |
| renaming `$abc$148$n258_1' to `_045_'. |
| renaming `$abc$148$n259_1' to `_046_'. |
| renaming `$abc$148$n261_1' to `_047_'. |
| renaming `$abc$148$n262_1' to `_048_'. |
| renaming `$abc$148$n264_1' to `_049_'. |
| renaming `$abc$148$n265_1' to `_050_'. |
| renaming `$abc$148$n267_1' to `_051_'. |
| renaming `$abc$148$n268_1' to `_052_'. |
| renaming `$abc$148$n270_1' to `_053_'. |
| renaming `$abc$148$n271_1' to `_054_'. |
| renaming `$abc$148$n273' to `_055_'. |
| renaming `$abc$148$n274' to `_056_'. |
| renaming `$abc$148$n276' to `_057_'. |
| renaming `$abc$148$n277_1' to `_058_'. |
| renaming `$abc$148$n279' to `_059_'. |
| renaming `$abc$148$n280_1' to `_060_'. |
| renaming `$abc$148$n282' to `_061_'. |
| renaming `$abc$148$n283' to `_062_'. |
| renaming `$abc$148$n285' to `_063_'. |
| renaming `$abc$148$n286' to `_064_'. |
| renaming `$abc$148$n288_1' to `_065_'. |
| renaming `$abc$148$n290_1' to `_066_'. |
| renaming `$abc$148$n291_1' to `_067_'. |
| renaming `$abc$148$n293_1' to `_068_'. |
| renaming `$abc$148$n294_1' to `_069_'. |
| renaming `$abc$148$n296_1' to `_070_'. |
| renaming `$abc$148$n297' to `_071_'. |
| renaming `$abc$148$n301' to `_072_'. |
| renaming `$abc$148$n302' to `_073_'. |
| renaming `$abc$148$n303' to `_074_'. |
| renaming `$abc$148$n305' to `_075_'. |
| renaming `$abc$148$n307' to `_076_'. |
| renaming `$abc$148$n309' to `_077_'. |
| renaming `$abc$148$n311' to `_078_'. |
| renaming `$abc$148$n313' to `_079_'. |
| renaming `$abc$148$n315' to `_080_'. |
| renaming `$abc$148$n317' to `_081_'. |
| renaming `$abc$148$n319' to `_082_'. |
| renaming `$abc$148$n321' to `_083_'. |
| renaming `$abc$148$n323' to `_084_'. |
| renaming `$abc$148$n325' to `_085_'. |
| renaming `$abc$148$n327' to `_086_'. |
| renaming `$abc$148$n329' to `_087_'. |
| renaming `$abc$148$n331' to `_088_'. |
| renaming `$abc$148$n333' to `_089_'. |
| renaming `$abc$148$n335' to `_090_'. |
| renaming `$abc$148$n336' to `_091_'. |
| renaming `$abc$148$n337' to `_092_'. |
| renaming `$abc$148$n338' to `_093_'. |
| renaming `$abc$148$n340' to `_094_'. |
| renaming `$abc$148$n342' to `_095_'. |
| renaming `$abc$148$n344' to `_096_'. |
| renaming `$abc$148$n346' to `_097_'. |
| renaming `$abc$148$n348' to `_098_'. |
| renaming `$abc$148$n350' to `_099_'. |
| renaming `$abc$148$n352' to `_100_'. |
| renaming `$abc$148$n354' to `_101_'. |
| renaming `$abc$148$n356' to `_102_'. |
| renaming `$abc$148$n358' to `_103_'. |
| renaming `$abc$148$n360' to `_104_'. |
| renaming `$abc$148$n362' to `_105_'. |
| renaming `$abc$148$n364' to `_106_'. |
| renaming `$abc$148$n366' to `_107_'. |
| renaming `$abc$148$n368' to `_108_'. |
| renaming `$abc$148$n370' to `_109_'. |
| renaming `$abc$148$n371' to `_110_'. |
| renaming `$abc$148$n372' to `_111_'. |
| renaming `$abc$148$n373' to `_112_'. |
| renaming `$abc$148$n374' to `_113_'. |
| renaming `$abc$148$n375' to `_114_'. |
| renaming `$procdff$100.V[0].ff' to `_307_'. |
| renaming `$procdff$101.V[0].ff' to `_308_'. |
| renaming `$procdff$102.V[0].ff' to `_309_'. |
| renaming `$procdff$103.V[0].ff' to `_310_'. |
| renaming `$procdff$103.V[1].ff' to `_311_'. |
| renaming `$procdff$103.V[2].ff' to `_312_'. |
| renaming `$procdff$103.V[3].ff' to `_313_'. |
| renaming `$procdff$103.V[4].ff' to `_314_'. |
| renaming `$procdff$103.V[5].ff' to `_315_'. |
| renaming `$procdff$103.V[6].ff' to `_316_'. |
| renaming `$procdff$103.V[7].ff' to `_317_'. |
| renaming `$procdff$104.V[0].ff' to `_318_'. |
| renaming `$procdff$105.V[0].ff' to `_319_'. |
| renaming `$procdff$106.V[0].ff' to `_320_'. |
| renaming `$procdff$107.V[0].ff' to `_321_'. |
| renaming `$procdff$107.V[1].ff' to `_322_'. |
| renaming `$procdff$107.V[2].ff' to `_323_'. |
| renaming `$procdff$107.V[3].ff' to `_324_'. |
| renaming `$procdff$107.V[4].ff' to `_325_'. |
| renaming `$procdff$107.V[5].ff' to `_326_'. |
| renaming `$procdff$107.V[6].ff' to `_327_'. |
| renaming `$procdff$107.V[7].ff' to `_328_'. |
| renaming `$procdff$108.V[0].ff' to `_329_'. |
| renaming `$procdff$108.V[1].ff' to `_330_'. |
| renaming `$procdff$108.V[2].ff' to `_331_'. |
| renaming `$procdff$108.V[3].ff' to `_332_'. |
| renaming `$procdff$108.V[4].ff' to `_333_'. |
| renaming `$procdff$108.V[5].ff' to `_334_'. |
| renaming `$procdff$108.V[6].ff' to `_335_'. |
| renaming `$procdff$108.V[7].ff' to `_336_'. |
| renaming `$procdff$109.V[0].ff' to `_337_'. |
| renaming `$procdff$110.V[0].ff' to `_338_'. |
| renaming `$procdff$110.V[10].ff' to `_339_'. |
| renaming `$procdff$110.V[11].ff' to `_340_'. |
| renaming `$procdff$110.V[12].ff' to `_341_'. |
| renaming `$procdff$110.V[13].ff' to `_342_'. |
| renaming `$procdff$110.V[14].ff' to `_343_'. |
| renaming `$procdff$110.V[15].ff' to `_344_'. |
| renaming `$procdff$110.V[1].ff' to `_345_'. |
| renaming `$procdff$110.V[2].ff' to `_346_'. |
| renaming `$procdff$110.V[3].ff' to `_347_'. |
| renaming `$procdff$110.V[4].ff' to `_348_'. |
| renaming `$procdff$110.V[5].ff' to `_349_'. |
| renaming `$procdff$110.V[6].ff' to `_350_'. |
| renaming `$procdff$110.V[7].ff' to `_351_'. |
| renaming `$procdff$110.V[8].ff' to `_352_'. |
| renaming `$procdff$110.V[9].ff' to `_353_'. |
| renaming `$procdff$111.V[0].ff' to `_354_'. |
| renaming `$procdff$111.V[1].ff' to `_355_'. |
| renaming `$procdff$111.V[2].ff' to `_356_'. |
| renaming `$procdff$111.V[3].ff' to `_357_'. |
| renaming `$procdff$112.V[0].ff' to `_358_'. |
| renaming `$procdff$114.V[0].ff' to `_359_'. |
| renaming `$procdff$115.V[0].ff' to `_360_'. |
| renaming `$procdff$116.V[0].ff' to `_361_'. |
| renaming `$procdff$116.V[10].ff' to `_362_'. |
| renaming `$procdff$116.V[11].ff' to `_363_'. |
| renaming `$procdff$116.V[12].ff' to `_364_'. |
| renaming `$procdff$116.V[13].ff' to `_365_'. |
| renaming `$procdff$116.V[14].ff' to `_366_'. |
| renaming `$procdff$116.V[15].ff' to `_367_'. |
| renaming `$procdff$116.V[1].ff' to `_368_'. |
| renaming `$procdff$116.V[2].ff' to `_369_'. |
| renaming `$procdff$116.V[3].ff' to `_370_'. |
| renaming `$procdff$116.V[4].ff' to `_371_'. |
| renaming `$procdff$116.V[5].ff' to `_372_'. |
| renaming `$procdff$116.V[6].ff' to `_373_'. |
| renaming `$procdff$116.V[7].ff' to `_374_'. |
| renaming `$procdff$116.V[8].ff' to `_375_'. |
| renaming `$procdff$116.V[9].ff' to `_376_'. |
| renaming `$procdff$117.V[0].ff' to `_377_'. |
| renaming `$procdff$117.V[10].ff' to `_378_'. |
| renaming `$procdff$117.V[11].ff' to `_379_'. |
| renaming `$procdff$117.V[12].ff' to `_380_'. |
| renaming `$procdff$117.V[13].ff' to `_381_'. |
| renaming `$procdff$117.V[14].ff' to `_382_'. |
| renaming `$procdff$117.V[15].ff' to `_383_'. |
| renaming `$procdff$117.V[1].ff' to `_384_'. |
| renaming `$procdff$117.V[2].ff' to `_385_'. |
| renaming `$procdff$117.V[3].ff' to `_386_'. |
| renaming `$procdff$117.V[4].ff' to `_387_'. |
| renaming `$procdff$117.V[5].ff' to `_388_'. |
| renaming `$procdff$117.V[6].ff' to `_389_'. |
| renaming `$procdff$117.V[7].ff' to `_390_'. |
| renaming `$procdff$117.V[8].ff' to `_391_'. |
| renaming `$procdff$117.V[9].ff' to `_392_'. |
| renaming `$procdff$99.V[0].ff' to `_393_'. |
| |
| READY. |
