src/Testcases/YosysTests/frontends/verilog_defaults/top1.v - third_party/Surelog - Git at Google

 module top1 (
 input [3:0] S,
 input [15:0] D,
 output M2,M4,M8,M16
 );

 endmodule
	module top1 (
	input [3:0] S,
	input [15:0] D,
	output M2,M4,M8,M16
	);

	endmodule