src/Testcases/YosysTests/misc/check/top.v - third_party/Surelog - Git at Google

 module top
     ( input d, clk, output reg q );

     wire u;


 	always @( posedge clk )
             q <= d;
 endmodule
	module top
	( input d, clk, output reg q );

	wire u;


	always @( posedge clk )
	q <= d;
	endmodule