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foss-fpga-tools
/
third_party
/
Surelog
/
4a79a47b7dd03dd4b2776ee40322b0149935d234
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_00194
/
top.v
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module
top
(
input a
,
output y
);
demo_sub
sub
(
y
,
,
1
'b1, a);
endmodule
module demo_sub(output y, z, input a, b);
assign y = a & b, z = a | b;
endmodule