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foss-fpga-tools
/
third_party
/
Surelog
/
4a79a47b7dd03dd4b2776ee40322b0149935d234
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_00195
/
top.v
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module
top
(
b
);
input b
;
wire a
=
100
_000
.
0
;
endmodule
