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foss-fpga-tools
/
third_party
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Surelog
/
4a79a47b7dd03dd4b2776ee40322b0149935d234
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_00635
/
top.v
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module
top
(
input clk
,
input rstn
,
input en
,
input
[
XLEN
-
1
:
0
]
d
,
output
[
XLEN
-
1
:
0
]
q
);
parameter XLEN
=
4
;