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foss-fpga-tools
/
third_party
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Surelog
/
4a79a47b7dd03dd4b2776ee40322b0149935d234
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_swap.ys
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read_verilog
../
top
.
v
extract
-
map
../
top
.
v
-
swap $dff D
,
CLK
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v
