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foss-fpga-tools
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third_party
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Surelog
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4a79a47b7dd03dd4b2776ee40322b0149935d234
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src
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Testcases
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YosysTests
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simple
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scripts
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shregmap_clkpol_any.ys
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read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
clkpol any
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v
