blob: f87af65143edad41486f6deeea2dfc6ee15e8408 [file] [log] [blame]
Skipping large tests
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START SURELOG REGRESSION
Starts on 11/15/2019 18:22:31
COMMAND: /usr/bin/time /home/alain/Surelog/src/Testcases/../dist/surelog/surelog
Creating release for regression...
Skipping ovm_pkg...
Skipping uvm_pkg...
Created dist/surelog_release_tcmalloc.tar.gz
PASS: surelog_release_tcmalloc
Run with mt=0
THERE ARE 103 tests
RUNNING 92 tests
+----------------------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
| TESTNAME | STATUS | FATALS | ERRORS | WARNINGS | NOTES | SYNTAX | ELAPSED TIME | MEM(Mb) |
+----------------------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
| UnitDefParam | PASS | 0 | 0 | 17 | 8 | 0 | 1s (+1s) | 39 |
| Monitor | PASS | 0 | 0 | 11 | 7 | 0 | 22s (+2s) | 265 |
| YosysSmall | PASS | 0 | 1 | 6 | 9 | 0 | 2s | 44 |
| UnitForLoop | PASS | 0 | 4 | 0 | 4 | 0 | 0s | 38 (-1) |
| SimpleVMM | PASS | 0 | 0 | 16 | 5 | 0 | 38s | 296 (-1) |
| SimpleUVM | PASS | 0 | 0 | 11 | 7 | 0 | 2s | 98 |
| YosysBigSimAes | PASS | 0 | 0 | 0 | 5 | 0 | 1s | 70 |
| UnitPackage | PASS | 0 | 0 | 6 | 9 | 0 | 2s | 55 |
| OldLibrary | PASS | 0 | 0 | 4 | 8 | 0 | 0s | 39 |
| SimpleCmdLineTest | PASS | 0 | 0 | 1 | 1 | 0 | 0s | 38 (-1) |
| YosysBigSimSoft | PASS | 0 | 0 | 2 | 6 | 0 | 3s | 107 |
| TimeUnit | PASS | 0 | 8 | 10 | 7 | 0 | 1s (+1s) | 46 |
| RiscV | PASS | 0 | 0 | 10 | 19 | 0 | 4s | 101 |
| SimpleClass | PASS | 0 | 1 | 2 | 6 | 0 | 0s | 39 |
| UnitAmiqEth | PASS | 0 | 0 | 7 | 4 | 0 | 9s (+2s) | 132 |
| PackageHierRef | PASS | 0 | 2 | 8 | 9 | 0 | 0s | 38 (-1) |
| AmiqEth | PASS | 0 | 10 | 32 | 5 | 0 | 29s (-5s) | 458 |
| SimpleInterface | PASS | 0 | 3 | 13 | 20 | 0 | 3s (+1s) | 97 (-1) |
| YosysOldI2c | PASS | 0 | 0 | 16 | 26 | 0 | 0s | 39 |
| Google | PASS | 0 | 169 | 83 | 114 | 39 | 16s | 697 (-1) |
| UnitLibrary | PASS | 0 | 2 | 16 | 31 | 0 | 0s | 39 |
| YosysDsp | PASS | 0 | 5 | 20 | 20 | 0 | 7s (+3s) | 110 |
| Icarus | PASS | 0 | 10 | 264 | 160 | 4 | 21s (+3s) | 675 (-1) |
| SimpleConstraint | PASS | 0 | 0 | 2 | 4 | 0 | 1s | 47 |
| UnitForeach | PASS | 0 | 7 | 0 | 4 | 0 | 0s | 41 |
| Escape | PASS | 0 | 5 | 10 | 8 | 0 | 0s | 44 |
| Scoreboard | PASS | 0 | 0 | 11 | 7 | 0 | 3s | 109 (-1) |
| BuildOVMPkg | PASS | 0 | 0 | 16 | 5 | 0 | 70s (+7s) | 821 (-1) |
| YosysOldSsPcm | PASS | 0 | 1 | 2 | 6 | 0 | 1s | 46 (-1) |
| YosysOldSimpleSpi | PASS | 0 | 2 | 7 | 9 | 0 | 1s | 76 |
| AVLMM | PASS | 0 | 4 | 4 | 5 | 0 | 3s (-2s) | 84 |
| UnitEnum | PASS | 0 | 1 | 2 | 5 | 0 | 0s | 38 (-1) |
| UnitQueue | PASS | 0 | 4 | 0 | 4 | 0 | 0s | 39 |
| TestMacros | PASS | 0 | 3 | 0 | 11 | 2 | 1s (+1s) | 41 |
| ApbSlave | PASS | 0 | 0 | 1 | 7 | 0 | 5s (+2s) | 62 |
| YosysOldOr | PASS | 0 | 0 | 0 | 117 | 0 | 15s (+3s) | 500 |
| SimpleParserTest | PASS | 0 | 0 | 0 | 0 | 0 | 3s (+1s) | 72 |
| YosysCam | PASS | 0 | 0 | 0 | 7 | 0 | 2s | 57 |
| ClassCons | PASS | 0 | 1 | 2 | 6 | 0 | 0s | 44 |
| TestBasic | PASS | 0 | 0 | 0 | 0 | 0 | 0s | 39 |
| SimpleOVM | PASS | 0 | 0 | 16 | 4 | 0 | 0s | 70 |
| AmiqSimpleTestSuite | PASS | 0 | 12 | 15 | 9 | 0 | 44s (+11s) | 528 |
| YosysVerx | PASS | 0 | 0 | 3 | 8 | 0 | 11s (+3s) | 229 |
| YosysBigSimOpenMsp | PASS | 0 | 7 | 33 | 33 | 1 | 6s (+1s) | 248 |
| TestFileSplit | PASS | 0 | 3 | 7 | 8 | 0 | 0s | 39 |
| SeqDriver | PASS | 0 | 0 | 11 | 7 | 0 | 5s (+1s) | 117 |
| MiniAmiq | PASS | 0 | 0 | 11 | 6 | 0 | 16s (+4s) | 251 (-1) |
| ClassFuncProto | PASS | 0 | 5 | 1 | 6 | 0 | 0s | 38 (-1) |
| UnitClass | PASS | 0 | 8 | 1 | 6 | 0 | 0s | 39 |
| SimpleIncludeAndMacros | PASS | 0 | 32 | 10 | 26 | 6 | 1s (+1s) | 45 |
| UnitSimpleIncludeAndMacros | PASS | 0 | 30 | 18 | 12 | 6 | 1s (+1s) | 45 |
| YosysBigSimAmber23 | PASS | 0 | 3 | 17 | 22 | 1 | 4s (+1s) | 215 |
| YosysOldAes | PASS | 0 | 6 | 6 | 10 | 0 | 3s | 178 (-1) |
| YosysOldUsb | PASS | 0 | 3 | 3 | 7 | 0 | 3s (+2s) | 70 |
| YosysOldOpen | PASS | 0 | 0 | 20 | 31 | 0 | 8s (+2s) | 159 (-1) |
| PragmaProtect | PASS | 0 | 1 | 1 | 6 | 0 | 0s | 41 (-1) |
| Custom_FIR_DMA | PASS | 0 | 7 | 54 | 102 | 0 | 11s (+3s) | 432 (-1) |
| UVMNestedSeq | PASS | 0 | 3 | 12 | 7 | 0 | 7s | 163 |
| YosysSmallBoom | PASS | 0 | 0 | 291 | 296 | 0 | 27s (-1s) | 2776 (+174) |
| GoogleMT | PASS | 0 | 169 | 83 | 114 | 39 | 17s (+3s) | 697 |
| InterfaceModPort | PASS | 0 | 0 | 2 | 15 | 0 | 1s | 46 |
| Yosys | PASS | 0 | 10 | 457 | 0 | 10 | 14s (+2s) | 369 |
| UnitElabBlock | PASS | 0 | 0 | 3 | 14 | 0 | 0s | 39 |
| DiffSimpleIncludeAndMacros | PASS | 0 | 62 | 30 | 39 | 0 | 1s | 47 (-1) |
| Ibex | PASS | 0 | 0 | 10 | 10 | 0 | 35s (+10s) | 504 (-1) |
| Verilator | PASS | 0 | 631 | 416 | 4 | 48 | 155s (+13s) | 2005 |
| UnitTest | PASS | 0 | 0 | 0 | 4 | 0 | 0s | 38 (-1) |
| YosysBigSimLm32 | PASS | 0 | 12 | 20 | 24 | 0 | 8s (+2s) | 296 |
| YosysOldSpi | PASS | 0 | 109 | 3 | 7 | 3 | 3s (+2s) | 124 (+1) |
| YosysBigSimReed | PASS | 0 | 1 | 15 | 11 | 0 | 2s | 111 (-1) |
| SVSwitch | PASS | 0 | 0 | 2 | 52 | 0 | 4s | 83 |
| CoresSweRV | PASS | 0 | 0 | 110 | 21 | 0 | 42s (+3s) | 793 (-1) |
| YosysOldSystem | PASS | 0 | 0 | 7 | 11 | 0 | 3s | 263 |
| OVMSwitch | PASS | 0 | 1 | 17 | 124 | 0 | 17s (+3s) | 282 (-1) |
| Driver | PASS | 0 | 0 | 11 | 8 | 0 | 4s | 122 (-1) |
| UtdSV | PASS | 0 | 9 | 2797 | 488 | 3 | 24s (+1s) | 1100 |
| YosysMarlann | PASS | 0 | 0 | 2 | 7 | 0 | 2s | 61 |
| UVMSwitch | PASS | 0 | 0 | 11 | 129 | 0 | 18s (+2s) | 309 |
| GenerateUnnamed | PASS | 0 | 0 | 2 | 24 | 0 | 0s | 39 |
| SplitFile | PASS | 0 | 13 | 17 | 27 | 0 | 0s | 46 |
| UnitElab | PASS | 0 | 1 | 17 | 2465 | 0 | 1s | 49 |
| SimpleTask | PASS | 0 | 0 | 2 | 20 | 0 | 1s | 45 (-1) |
| UnitElabExternNested | PASS | 0 | 0 | 8 | 22 | 0 | 0s | 39 |
| BlackParrot | PASS | 0 | 15 | 219 | 108 | 0 | 65s (+10s) | 1208 (-1) |
| IbexGoogle | PASS | 0 | 7 | 11 | 7 | 1 | 44s (+4s) | 516 |
| BeginKeywords | PASS | 0 | 0 | 1 | 6 | 0 | 0s | 39 |
| YosysBigSimPong | PASS | 0 | 0 | 6 | 8 | 0 | 3s (+1s) | 127 (-1) |
| YosysOldSasc | PASS | 0 | 3 | 3 | 9 | 0 | 2s (+1s) | 64 (-1) |
| SimpleClass1 | PASS | 0 | 8 | 15 | 8 | 0 | 2s (+1s) | 98 |
| SimpleClass2 | PASS | 0 | 2 | 3 | 4 | 0 | 0s | 39 |
| UnitPython | PASS | 0 | 0 | 3 | 0 | 0 | 0s | 38 (-1) |
| LibraryIntercon | PASS | 0 | 0 | 3 | 29 | 0 | 1s | 44 |
+----------------------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
RESULT : PASS
+--------------+----------+----------+
| | CURRENT | PREVIOUS |
+--------------+----------+----------+
|TOTAL ELAPSED | 882s | 775s |
|TOTAL USER | 953s | 842s |
|MAX MEM TEST | 2776Mb | 2602Mb |
|MAX TIME TEST | 155s | 142s |
+--------------+----------+----------+
End on 11/15/2019 18:38:02
END SURELOG REGRESSION
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