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chapter-6
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6.10--implicit_port.sv
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/*
:name: implicit_port
:description: implicit port signal tests
:should_fail: 0
:tags: 6.10
*/
module
top
(
input
[
3
:
0
]
a
,
input
[
3
:
0
]
b
);
wire
[
3
:
0
]
c
;
assign c
=
a
|
b
;
endmodule
