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foss-fpga-tools
/
third_party
/
Surelog
/
5074a001626fcee109f97975f5d7756bd1e05f5d
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_00862
/
top.v
blob: 60063f2136205bfd20c904798362bf81b9b0e30e [
file
]
module
test
(
input wire A
);
localparam TEST
=
1
;
always_comb
begin
case
(
A
)
TEST
:
assert
(
1
);
endcase
end
endmodule