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foss-fpga-tools
/
third_party
/
Surelog
/
5074a001626fcee109f97975f5d7756bd1e05f5d
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
design_import.ys
blob: e6fca77b432e79639bc454384b959675a06f9403 [
file
]
read_verilog
../
top
.
v
proc
design
-
save top
design
-
import
top
write_verilog synth
.
v
