blob: b7ffdcf7a8390f8abcd5546c7ed56040a8d40d55 [file] [log] [blame]
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* SURELOG System Verilog Compiler/Linter *
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|-------|------------------|-------------------|
| | FILE UNIT COMP | ALL COMPILATION |
|-------|------------------|-------------------|
| FATAL | 0 | 0 |
| ERROR | 30 | 32 |
|WARNING| 19 | 11 |
| INFO | | |
| NOTE | 12 | 26 |
|-------|------------------|-------------------|
FILE UNIT LOG: ./slpp_unit/surelog.log
ALL FILES LOG: ./slpp_all/surelog.log
DIFFS:
./slpp_unit/work/top_3.v and ./slpp_all/work/top_3.v
./slpp_unit/work/top_4.v and ./slpp_all/work/top_4.v
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* End SURELOG SVerilog Compiler/Linter *
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1.03user 0.04system 0:01.28elapsed 83%CPU (0avgtext+0avgdata 50016maxresident)k
1184inputs+368outputs (1major+21757minor)pagefaults 0swaps