| commit | 98cfc38b965a5eb40ff4d27ba845d6a2c57c9a3f | [log] [tgz] |
|---|---|---|
| author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Sat Nov 16 10:04:51 2019 -0800 |
| committer | GitHub <noreply@github.com> | Sat Nov 16 10:04:51 2019 -0800 |
| tree | 5e9d672e645297a356ff80eb41c1fe570dbe52ac | |
| parent | f29b69094ae895a3554f5825faba07ba868f4fc8 [diff] | |
| parent | 34d363c09ff73119afca2b421d9dd458c0d6af8a [diff] |
Merge pull request #60 from alainmarcel/alainmarcel-patch-1 Readme updates and stop regression auto updates
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output