SVIncCompil/Testcases/YosysTests/regression/issue_00763/top.v - third_party/Surelog - Git at Google

 module top(input clk, a, b);
   always @(posedge clk)
     if (a) begin :scope
       reg b_inv = ~b;
     end
 endmodule
	module top(input clk, a, b);
	always @(posedge clk)
	if (a) begin :scope
	reg b_inv = ~b;
	end
	endmodule