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foss-fpga-tools
/
third_party
/
Surelog
/
5d8813c36fc3561ecb4c6ab9a579c7fbcb8e2d87
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01118
/
top.v
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module
top
(
output
[
3
:
0
]
o
);
generate
genvar i
;
for
(
i
=
3
;
i
>=
0
;
i
=
i
-
1
)
begin
assign o
[
i
]
=
1
'b0;
end
endgenerate
endmodule
