SVIncCompil/Testcases/YosysTests/regression/issue_01291/top.v - third_party/Surelog - Git at Google

 module frozen(clk, out);

    input        clk;
    output reg   out;

    always @(posedge clk) begin
       out <= out;
    end

 endmodule // frozen
	module frozen(clk, out);

	input clk;
	output reg out;

	always @(posedge clk) begin
	out <= out;
	end

	endmodule // frozen