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foss-fpga-tools
/
third_party
/
Surelog
/
6ce6840a96fc0d4401dbc401b0aecc29d7234654
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
design_import.ys
blob: e6fca77b432e79639bc454384b959675a06f9403 [
file
]
read_verilog
../
top
.
v
proc
design
-
save top
design
-
import
top
write_verilog synth
.
v
