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foss-fpga-tools
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Surelog
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6d4537db9a43278cd140791509f0507db4827abe
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SVIncCompil
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Testcases
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YosysTests
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simple
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scripts
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opt_lut_dlogic.ys
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read_verilog
../
top
.
v
synth_ice40
opt_lut
-
dlogic $_ANDNOT_
:
A
=
I0
design
-
reset
read_verilog
../
top
.
v
synth
-
top top
write_verilog synth
.
v
