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foss-fpga-tools
/
third_party
/
Surelog
/
6e9a914a8fa2b72a38fb9e60ef2c0c34df436b4a
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sim_clock.ys
blob: 19f31d7a01cd688e5ef587bd284bb354dfe3d572 [
file
]
read_verilog
-
sv
../
top
.
v
proc
tee
-
o result
.
log sim
-
clock x top
