| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
| |
| [INFO :CM0023] Creating log file ../../build/tests/SimpleCmdLineTest/slpp_all/surelog.log. |
| |
| [WARNI:CM0010] Command line argument "-bad" ignored. |
| |
| [NOTE :CM0009] Command line argument "+libreorder" ignored. |
| |
| [INFO :PP0122] Preprocessing source file "builtin.sv". |
| |
| [INFO :PP0122] Preprocessing source file "top.v". |
| |
| [INFO :PP0122] Preprocessing source file "/home/alain/Surelog/tests/SimpleCmdLineTest/cell.v". |
| |
| [INFO :PA0201] Parsing source file "builtin.sv". |
| |
| [INFO :PA0201] Parsing source file "top.v". |
| |
| [INFO :PA0201] Parsing source file "/home/alain/Surelog/tests/SimpleCmdLineTest/cell.v". |
| |
| [WARNI:PA0205] top.v:1 No timescale set for "top". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleCmdLineTest/cell.v:1 No timescale set for "out". |
| |
| [ FATAL] : 0 |
| [ ERROR] : 0 |
| [WARNING] : 3 |
| [ NOTE] : 1 |
| |
| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 0.11user 0.02system 0:00.15elapsed 96%CPU (0avgtext+0avgdata 40220maxresident)k |
| 0inputs+96outputs (0major+9896minor)pagefaults 0swaps |
