blob: 4394b97df482a90786262bef2d18f50dc7bc589b [file] [log] [blame]
// DESCRIPTION: Verilator: Verilog Test module
module t;
initial begin
// verilator lint_off FUTURE1
$write("*-* All Finished *-*\n");
$finish;
// verilator FUTURE2
// verilator FUTURE2 blah blah
end
endmodule