| read_verilog ../squarediffmacc.v | |
| hierarchy -top squarediffmacc | |
| proc | |
| flatten | |
| equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check | |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | |
| cd squarediffmacc | |
| #Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. | |
| stat | |
| select -assert-count 1 t:BUFG | |
| select -assert-count 64 t:FDRE | |
| select -assert-count 78 t:LUT2 | |
| select -assert-count 7 t:LUT3 | |
| select -assert-count 11 t:LUT4 | |
| select -assert-count 8 t:LUT5 | |
| select -assert-count 125 t:LUT6 | |
| select -assert-count 44 t:MUXCY | |
| select -assert-count 50 t:MUXF7 | |
| select -assert-count 17 t:MUXF8 | |
| select -assert-count 47 t:XORCY | |
| select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D |