Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
76425fe9c1b685310008913d97503847d2f7f72e
/
.
/
src
/
Testcases
/
YosysTestSuite
/
errors
/
syntax_err09.v
blob: 1e472eb94ae9d0283aecd18824b50d5e458ea338 [
file
] [
log
] [
blame
]
module
a
(
input wire x
=
1
'b0);
endmodule