Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
76425fe9c1b685310008913d97503847d2f7f72e
/
.
/
src
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sim_clock.ys
blob: 19f31d7a01cd688e5ef587bd284bb354dfe3d572 [
file
] [
log
] [
blame
]
read_verilog
-
sv
../
top
.
v
proc
tee
-
o result
.
log sim
-
clock x top
