blob: ed1b46f01222e092e91744c445e1edc6a3516f46 [file] [log] [blame]
********************************************
* SURELOG System Verilog Compiler/Linter *
********************************************
[INFO :CM0023] Creating log file ./slpp_all/surelog.log.
[WARNI:CM0010] Command line argument "-bad" ignored.
[NOTE :CM0009] Command line argument "+libreorder" ignored.
[INFO :PP0122] Preprocessing source file "/home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv".
[INFO :PP0122] Preprocessing source file "top.v".
[INFO :PP0122] Preprocessing source file "/home/alain/Surelog/SVIncCompil/Testcases/SimpleCmdLineTest/cell.v".
[ FATAL] : 0
[ ERROR] : 0
[WARNING] : 1
[ NOTE] : 1
********************************************
* End SURELOG SVerilog Compiler/Linter *
********************************************
0.13user 0.02system 0:00.27elapsed 55%CPU (0avgtext+0avgdata 45900maxresident)k
32inputs+32outputs (0major+10071minor)pagefaults 0swaps