| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
| |
| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
| |
| [INFO :CM0020] Separate compilation-unit mode is on. |
| |
| [ERROR:PA0207] top.v:9 Syntax error: no viable alternative at input 'module top();\n wire context;\n\n enmodule\n \n', |
| . |
| |
| [WARNI:PA0205] top.v:4 No timescale set for "MODULE NAME UNKNOWN". |
| |
| [INFO :CP0300] Compilation... |
| |
| [INFO :EL0526] Design Elaboration... |
| |
| [NOTE :EL0503] top.v:4 Top level module "work@MODULE NAME UNKNOWN". |
| |
| [NOTE :EL0508] Nb Top level modules: 0. |
| |
| [NOTE :EL0509] Max instance depth: 0. |
| |
| [NOTE :EL0510] Nb instances: 0. |
| |
| [NOTE :EL0511] Nb leaf instances: 0. |
| |
| [ FATAL] : 0 |
| [ ERROR] : 1 |
| [WARNING] : 1 |
| [ NOTE] : 5 |
| |
| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 0.20user 0.02system 0:00.43elapsed 53%CPU (0avgtext+0avgdata 45736maxresident)k |
| 8inputs+16outputs (0major+10098minor)pagefaults 0swaps |
