| ******************************************** | |
| * SURELOG System Verilog Compiler/Linter * | |
| ******************************************** | |
| |-------|------------------|-------------------| | |
| | | FILE UNIT COMP | ALL COMPILATION | | |
| |-------|------------------|-------------------| | |
| | FATAL | 0 | 0 | | |
| | ERROR | 30 | 32 | | |
| |WARNING| 19 | 11 | | |
| | INFO | | | | |
| | NOTE | 12 | 26 | | |
| |-------|------------------|-------------------| | |
| FILE UNIT LOG: ../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/surelog.log | |
| ALL FILES LOG: ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/surelog.log | |
| DIFFS: | |
| ../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/work/top_3.v and ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/work/top_3.v | |
| ../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/work/top_4.v and ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/work/top_4.v | |
| ******************************************** | |
| * End SURELOG SVerilog Compiler/Linter * | |
| ******************************************** | |
| 1.03user 0.02system 0:01.08elapsed 98%CPU (0avgtext+0avgdata 46180maxresident)k | |
| 1152inputs+376outputs (3major+21615minor)pagefaults 0swaps |