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foss-fpga-tools
/
third_party
/
Surelog
/
861ed7dc3ad91ddad1bf155cd28bdc110f3a5abb
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00195
/
top.v
blob: 19ddbfcd78acdaf8571451f2a0493e2ecca64af2 [
file
]
module
top
(
b
);
input b
;
wire a
=
100
_000
.
0
;
endmodule
