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foss-fpga-tools/third_party/Surelog/8bea0781c44e5ebbeab5135503fd4ff8b9daec3b/./SVIncCompil/Testcases/YosysBigSim/bch_verilog/sim
tree: 9606ccac05f3762b1c6bb63281d3e8f5c427474a
  1. settings.sh
  2. sim.v
  3. tb_sim.v