Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
8bea0781c44e5ebbeab5135503fd4ff8b9daec3b
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01217
/
top.v
blob: fbdffd5b7505e9a1d23fcf6b5f977bf3f371450c [
file
] [
log
] [
blame
]
`default_nettype none
module mcve2(david);
output reg david;
always @(*)
goliath = 4;
always @(*)
david = goliath;
endmodule
`
default_nettype wire
