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foss-fpga-tools
/
third_party
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Surelog
/
8bea0781c44e5ebbeab5135503fd4ff8b9daec3b
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
shregmap_match.ys
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read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
match \GP_DFF
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v
