Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
91c065df031c31bc350c1052607ca347e71c741d
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
design_import.ys
blob: e6fca77b432e79639bc454384b959675a06f9403 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
design
-
save top
design
-
import
top
write_verilog synth
.
v
