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foss-fpga-tools
/
third_party
/
Surelog
/
91c065df031c31bc350c1052607ca347e71c741d
/
.
/
src
/
Testcases
/
YosysTests
/
verific
/
opers
/
rednor.sv
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module
top
(
input
[
6
:
0
]
a
,
output y
);
assign y
=
~|
a
;
endmodule
