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foss-fpga-tools
/
third_party
/
Surelog
/
98dd329c028fec285730d65e09a31eaf63609ccb
/
.
/
src
/
Testcases
/
Icarus
/
ivltests
/
pr509.v
blob: 7c9f52aba2da49521ce4c437760d3e5dba933692 [
file
]
/*
* Make sure the degenerate case that a wire is linked to itself
* is handled properly.
*/
module
example
;
wire w
;
assign w
=
w
;
initial $display
(
"PASSED"
);
endmodule